High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips. - Jae-Tack Yoo; Ganesh Gopalakrishnan; Kent F. Smith; V. John Mathews (ARVLSI, 1995)

Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs. - Jae-Tack Yoo; Erik Brunvand; Kent F. Smith (Great Lakes Symposium on VLSI, 1995)

A fast parallel squarer based on divide-and-conquer. - Jae-Tack Yoo; Kent F. Smith; Ganesh Gopalakrishnan (IEEE J. Solid State Circuits, 1997)

Timing constraints for high-speed counterflow-clocked pipelining. - Jae-Tack Yoo; Ganesh Gopalakrishnan; Kent F. Smith (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Low-power digital filtering using approximate processing with variable canonic signed digit coefficients. - Young-Woo Kim; Young-Mo Yang; Jae-Tack Yoo; Soo-Won Kim (ISCAS, 2000)

Dual-Output Trans-Impedance Amplifier of Cost-effective CMOS Optical Receiver for Digital Audio Interfaces. - Kyu-Young Kim; Kwansu Shon; Soo-Won Kim; Jae-Tack Yoo (ISCAS, 2007)

A continuous-time equalizer adopting a clock attenuation tracking technique for digital display interface (DDI). - Kyu-Young Kim; Jae-Tack Yoo; Soo-Won Kim (IEICE Electron. Express, 2007)

A reliable CMOS 16: 1 binary-tree multiplexer applying delay compensation techniques. - Kwansu Shon; Jae-Tack Yoo; Soo-Won Kim (IEICE Electron. Express, 2007)

Reduced Energy-Ratio Measure for Robust Autofocusing in Digital Camera. - Sang-Yong Lee; Jae-Tack Yoo; Yogendera Kumar; Soo-Won Kim (IEEE Signal Process. Lett., 2009)