A 1.4 V 10-bit 20 MSPS pipelined A/D converter. - Hee-Cheol Choi; Ho-Jin Park; Shin-Kyu Bae; Jae-Whui Kim; Philip Chung 003 (ISCAS, 2000)

A DLL based 10-320 MHz clock synchronizer. - Sung-Sik Hwang; Ki-Mo Joo; Ho-Jin Park; Jae-Whui Kim; Philip Chung 003 (ISCAS, 2000)

A 2.4 V, 12 mW stereo audio D/A converter with double sampling switching. - Nam-Keal Kim; Wang-Seup Yeum; Jae-Whui Kim (ISCAS, 2000)

A 1 mW 10-bit 500KSPS SAR A/D converter. - Jaejin Park; Ho-Jin Park; Jae-Whui Kim; Sangnam Seo; Philip Chung 003 (ISCAS, 2000)

A 3.3 V 14-bit 10 MSPS calibration-free CMOS pipelined A/D converter. - Seung-Bin You; Ku-Whan Lee; Hee-Cheol Choi; Ho-Jin Park; Jae-Whui Kim; Philip Chung 003 (ISCAS, 2000)

Digitally tuneable on-chip resistor in CMOS for high-speed data transmission. - Kyoung-Hoi Koo; Jin-Ho Seo; Jae-Whui Kim (ISCAS (1), 2003)

A slew-rate controlled output driver using PLL as compensation circuit. - Soon-Kyun Shin; Seok-Min Jung; Jin-Ho Seo; Myeong-Lyong Ko; Jae-Whui Kim (IEEE J. Solid State Circuits, 2003)

A CMOS 16-bit 20MSPS analog front end for scanner/MFP applications. - Seung-Bin You; Jae-Whui Kim; Suki Kim (IEEE Trans. Consumer Electron., 2003)

A 2W, 92% efficiency and 0.01% THD+N class-D audio power amplifier for mobile applications, based on the novel SCOM architecture. - Soo-Hyoung Lee; Jae-Young Shin; Ho-Young Lee; Ho-Jin Park; Kristian L. Lund; Karsten Nielsen; Jae-Whui Kim (CICC, 2004)

A 1.8V 8-bit 250Msample/s Nyquist-rate CMOS pipelined ADC. - Tae-Hwan Oh; Ho-Young Lee; Ho-Jin Park; Jae-Whui Kim (ISCAS (1), 2004)

A new level shifter in ultra deep sub-micron for low to wide range voltage applications. - Kyoung-Hoi Koo; Jin-Ho Seo; Myeong-Lyong Ko; Jae-Whui Kim (SoCC, 2004)

A high current driving charge pump with current regulation method. - Soon-Kyun Shin; Bai-Sun Kong; Chil-Gee Lee; Young-Hyun Jun; Jae-Whui Kim (CICC, 2005)

A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature. - Soon-Kyun Shin; Wang Yu; Bai-Sun Kong; Chil-Gee Lee; Young-Hyun Jun; Jae-Whui Kim (CICC, 2005)

A new level-up shifter for high speed and wide range interface in ultra deep sub-micron. - Kyoung-Hoi Koo; Jin-Ho Seo; Myeong-Lyong Ko; Jae-Whui Kim (ISCAS (2), 2005)

A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors. - Young-Jae Cho; Kyung-Hoon Lee; Hee-Cheol Choi; Seung-Hoon Lee 006; Kyoung-Ho Moon; Jae-Whui Kim (CICC, 2006)

A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure. - Yong-Hee Lee; Moo-Yeol Choi; Seung-Bin You; Wang-Seup Yeum; Ho-Jin Park; Jae-Whui Kim (CICC, 2006)

A versatile I/O with robust impedance calibration for various memory interfaces. - Kyoung-Hoi Koo; Soo-Kyung Lee; Jin-Ho Seo; Myeong-Lyong Ko; Jae-Whui Kim (ISCAS, 2006)

A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm2. - Tae-Hwan Oh; Sang-Min Yoo; Kyoung-Ho Moon; Jae-Whui Kim (ISCAS, 2006)

A 3.0V 12b 120 Msample/s CMOS pipelined ADC. - Sang-Min Yoo; Tae-Hwan Oh; Ho-Young Lee; Kyung-Ho Moon; Jae-Whui Kim (ISCAS, 2006)

A 15mW 0.2mm2 50MS/s ADC with wide input range. - Hee-Cheol Choi; Ju-Wha Kim; Sang-Min Yoo; Kang-Jin Lee; Tae-Hwan Oh; Mi-Jung Seo; Jae-Whui Kim (ISSCC, 2006)

An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface. - Jun-Hyun Bae; Jin-Ho Seo; Hwan-Seok Yeo; Jae-Whui Kim; Jae-Yoon Sim; Hong-June Park (CICC, 2007)

A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC. - Young-Ju Kim; Hee-Cheol Choi; Si-Wook Yoo; Seung-Hoon Lee 006; Dae-Young Chung; Kyoung-Ho Moon; Ho-Jin Park; Jae-Whui Kim (CICC, 2007)

A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration. - Ho-Young Lee; Tae-Hwan Oh; Ho-Jin Park; Hae-Seung Lee; Mark Spaeth; Jae-Whui Kim (CICC, 2007)

Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations. - Soon-Kyun Shin; Wang Yu; Young-Hyun Jun; Jae-Whui Kim; Bai-Sun Kong; Chil-Gee Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control. - Moo-Yeol Choi; Sung-No Lee; Seung-Bin You; Wang-Seup Yeum; Ho-Jin Park; Jae-Whui Kim; Hae-Seung Lee (CICC, 2008)

A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling. - Kang-Jin Lee; Kyoung-Jun Moon; Kwang-Sung Ma; Kyoung-Ho Moon; Jae-Whui Kim (CICC, 2008)

A 16b 10MS/s digitally self-calibrated ADC with time constant control. - Tae-Hwan Oh; Ho-Young Lee; Ju-Hwa Kim; Ho-Jin Park; Kyoung-Ho Moon; Jae-Whui Kim; Hae-Seung Lee (CICC, 2008)

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC. - Min-Gyu Kim; Gil-Cho Ahn; Pavan Kumar Hanumolu; Sanghyeon Lee; Sang-Ho Kim; Seung-Bin You; Jae-Whui Kim; Gabor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2008)

An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing. - Sunwoo Kwon; Pavan Kumar Hanumolu; Sang-Ho Kim; Sung-No Lee; Seung-Bin You; Ho-Jin Park; Jae-Whui Kim; Un-Ku Moon (CICC, 2009)