A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS. - Jae-Won Nam; Young-Deuk Jeon; Young-Kyun Cho; Sang-Gug Lee 001; Jong-Kee Kwon (ESSCIRC, 2009)

A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS. - Young-Deuk Jeon; Young-Kyun Cho; Jae-Won Nam; Kwi-Dong Kim; Woo-Yol Lee; Kuk-Tae Hong; Jong-Kee Kwon (CICC, 2010)

A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique. - Young-Kyun Cho; Young-Deuk Jeon; Jae-Won Nam; Jong-Kee Kwon (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS. - Jae-Won Nam; Young-Deuk Jeon; Seok-Ju Yun; Tae Moon Roh; Jong-Kee Kwon (ISOCC, 2011)

A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications. - Young-Kyun Cho; Young-Deuk Jeon; Jae-Won Nam; Jong-Kee Kwon (Microelectron. J., 2011)

A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique. - Jae-Won Nam; Young-Deuk Jeon; Young-Kyun Cho; Jong-Kee Kwon (Microelectron. J., 2011)

A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture. - Young-Deuk Jeon; Jae-Won Nam; Kwi-Dong Kim; Tae Moon Roh; Jong-Kee Kwon (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS. - Jae-Won Nam; David Chiong; Mike Shuo-Wei Chen (CICC, 2013)

A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. - Jae-Won Nam; Mohsen Hassanpourghadi; Aoyang Zhang; Mike Shuo-Wei Chen (VLSI Circuits, 2016)

An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS. - Jae-Won Nam; Mike Shuo-Wei Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation. - Jae-Won Nam; Mohsen Hassanpourghadi; Aoyang Zhang; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2018)

A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS. - Jae-Won Nam; Mike Shuo-Wei Chen (CICC, 2019)

A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer. - Jae-Won Nam; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2020)

HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks. - Soowang Park; Jae-Won Nam; Sandeep K. Gupta 001 (ASP-DAC, 2021)

Generative Adversarial Attacks on Fingerprint Recognition Systems. - Hee won Kwon; Jae-Won Nam; Joongheon Kim; Youn Kyu Lee (ICOIN, 2021)

Machine-Learning based Analog and Mixed-signal Circuit Design and Optimization. - Jae-Won Nam; Youn Kyu Lee (ICOIN, 2021)

Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique. - Jae-Won Nam; Ju-Hyeok Ahn; Jong-Phil Hong (IEEE Access, 2022)

A Low-Power Class-C Voltage-Controlled Oscillator With Robust Start-Up and Compact High-Q Capacitor Array. - Young-Kyun Cho; Jae-Won Nam; Sang-Won Lee 007 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Regression Model-based VCO Design Optimization Technique. - Jin-Won Hyun; Jae-Won Nam (ICEIC, 2023)

AMS Circuit Design Optimization Technique Based on ANN Regression Model With VAE Structure. - Jin-Won Hyun; Jae-Won Nam (IEEE Access, 2023)

Analysis of Quarter Method Applied ROM-Based DDFS Architecture. - Jae-Yun Park; Su-Hyeon Kim; Hyunyoung Yoo; Jae-Won Nam (IEEE Access, 2023)

Optimizing EV Chargers Location via Integer Programming. - Seungmo Kim; Yeonho Jeong; Jae-Won Nam (CoRR, 2023)

High-Speed Light Detection Sensor for Hardware Security in Standard CMOS Technology. - Dana Kim; Jong-Phil Hong; Jiwon Lee; Jae-Won Nam (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

AI-Assisted Design Automation of Circular and Asymmetric Inductor in CMOS Technology. - Jin-Won Hyun; Dana Kim; Kyung-Sik Choi; Jae-Won Nam (ISOCC, 2024)

A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control. - Jae-Yun Park; Jae-Won Nam (IEEE Trans. Circuits Syst. II Express Briefs, 2024)