Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model. - Young-Gu Kim; Sang-Hoon Lee; Dae-Han Kim; Jae-Woo Im; Sung-Eun Yu; Dae-Wook Kim; Young-Kwan Park; Jeong-Taek Kong (ISQED, 2006)

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate. - Jae-Woo Im; Woopyo Jeong; Doo-Hyun Kim; Sangwan Nam; Dong-Kyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Youse Kim; Hyun Wook Park; Dong-Hun Kwak; Sang-Won Park; et al. (ISSCC, 2015)

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate. - Woopyo Jeong; Jae-Woo Im; Doo-Hyun Kim; Sangwan Nam; Dong-Kyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Youse Kim; Hyun Wook Park; Dong-Hun Kwak; Sang-Won Park; et al. (IEEE J. Solid State Circuits, 2016)

Early HW/SW Co-Verification Using Virtual Platforms. - Jungyun Choi; Kyungsu Kang; Byunghoon Lee; Sangho Park; Jae-Woo Im (ISOCC, 2021)

Toward Heterogeneous Virtual Platforms For Early SW Development. - Dongyoung Lee; Kyungsu Kang; Jongseong Park; Byunghoon Lee; Jinbeom Kim; Jae-Woo Im (ISOCC, 2022)

30.1 A 28Gb/mm24XX-Layer 1Tb 3b/Cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/Pin IOs. - Sang-Soo Park; Jaedoeg Lyu; Myungjun Kim; Jaeyun Lee; Youngsun Song; Chungho Yu; Makoto Hirano; Yongseok Kwon; Jonghoon Park; Hojoon Kim; Daein Lee; Donghyun Seo; et al. (ISSCC, 2025)