Analysis and prevention of DRAM latch-up during power-on. - Young-Hee Kim; Jae-Yoon Sim; Hong June Park; Jae-Ik Doh; Kun-Woo Park; Hyun-Woong Chung; Jong-Hoon Oh; Choon-Sik Oh; Seung-Han Ahn (IEEE J. Solid State Circuits, 1997)

A 1-Gb/s bidirectional I/O buffer using the current-mode scheme. - Jae-Yoon Sim; Young-Soo Sohn; Seung-Chan Heo; Hong-June Park; Soo-In Cho (IEEE J. Solid State Circuits, 1999)

A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme. - Jae-Yoon Sim; Jang-Jin Nam; Young-Soo Sohn; Hong-June Park; Chang-Hyun Kim; Soo-In Cho (IEEE J. Solid State Circuits, 2002)

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor. - Jae-Yoon Sim; Hongil Yoon; Ki-Chul Chun; Hyun-Seok Lee; Sang-Pyo Hong; Kyu-Chan Lee; Jei-Hwan Yoo; Dong-Il Seo; Soo-In Cho (IEEE J. Solid State Circuits, 2003)

Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs. - Jae-Yoon Sim; Kee-Won Kwon; Ki-Chul Chun (IEEE J. Solid State Circuits, 2004)

Multilevel differential encoding with precentering for high-speed parallel link transceiver. - Jae-Yoon Sim; Won Namgoong (IEEE J. Solid State Circuits, 2005)

DC-Balanced Block Inversion Coding for High-Speed Links. - Jae-Yoon Sim (IEICE Trans. Electron., 2006)

An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface. - Jun-Hyun Bae; Jin-Ho Seo; Hwan-Seok Yeo; Jae-Whui Kim; Jae-Yoon Sim; Hong-June Park (CICC, 2007)

A 40-to-800MHz Locking Multi-Phase DLL. - Young-Sang Kim; Seung-Jin Park; Yong-Sub Kim; Dong-Bi Jang; Seh-Woong Jeong; Hong-June Park; Jae-Yoon Sim (ISSCC, 2007)

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator. - Young-Chan Jang; Jun-Hyun Bae; Sang-Hune Park; Jae-Yoon Sim; Hong-June Park (IEICE Trans. Electron., 2007)

Segmented Group-Inversion Coding for Parallel Links. - Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A low-voltage OP amp with digitally controlled algorithmic approximation. - Dong-Woo Jee; Seung-Jin Park; Hong-June Park; Jae-Yoon Sim (CICC, 2008)

A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration. - Hyung-Joon Chi; Jae-Seung Lee; Seong-Hwan Jeon; Seung-Jun Bae; Jae-Yoon Sim; Hong-June Park (ISSCC, 2008)

Deadzone-Minimized Systematic Offset-Free Phase Detectors. - Young-Sang Kim; Yunjae Suh; Hong-June Park; Jae-Yoon Sim (IEICE Trans. Electron., 2008)

A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface. - Sang-Hune Park; Kwang-Hee Choi; Jung-Bum Shin; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate. - Seon-Kyoo Lee; Young-Sang Kim; Hyunsoo Ha; Young Hun Seo; Hong-June Park; Jae-Yoon Sim (ISSCC, 2009)

A Distortion-Free General Purpose LVDS Driver. - Seung-Jin Park; Young Hun Seo; Hong-June Park; Jae-Yoon Sim (IEICE Trans. Electron., 2009)

A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control. - Hae-Kang Jung; Kyoungho Lee; Jong-Sam Kim; Jae-Jin Lee; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2009)

A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling. - Seung-Jun Bae; Hyung-Joon Chi; Young-Soo Sohn; Jae-Seung Lee; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL. - Kwang-Hee Choi; Jung-Bum Shin; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel. - Jun-Hyun Bae; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Jae-Yoon Sim; Hong-June Park (CICC, 2010)

A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines. - Hae-Kang Jung; Soo-Min Lee; Jae-Yoon Sim; Hong-June Park (CICC, 2010)

A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS. - Seon-Kyoo Lee; Young Hun Seo; Yunjae Suh; Hong-June Park; Jae-Yoon Sim (ISSCC, 2010)

A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch Calibration. - Jun-Hyun Bae; Sang-Hune Park; Jae-Yoon Sim; Hong-June Park (IEICE Trans. Electron., 2010)

An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation. - Young-Sang Kim; Yunjae Suh; Hong-June Park; Jae-Yoon Sim (IEICE Trans. Electron., 2010)

A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage Using VCDL and Time-to-Digital Converter. - Jae-Seung Lee; Jae-Yoon Sim; Hong-June Park (IEICE Trans. Electron., 2010)

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS. - Seon-Kyoo Lee; Young Hun Seo; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2010)

A 5 Gb/s Transmitter With a TDR-Based Self-Calibration of Preemphasis Strength. - Young Hun Seo; Young-Sang Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio. - Hye-Jung Kwon; Jae-Seung Lee; Jae-Yoon Sim; Hong-June Park (A-SSCC, 2011)

Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC. - Ji-Yong Um; Jae-Hwan Kim; Jae-Yoon Sim; Hong-June Park (A-SSCC, 2011)

Time-interleaved sample clock generator for ultrasound beamformer application. - Jae-Hwan Kim; Ji-Yong Um; Jae-Yoon Sim; Hong-June Park (ISOCC, 2011)

A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering. - Dong-Woo Jee; Yunjae Suh; Hong-June Park; Jae-Yoon Sim (ISSCC, 2011)

A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition. - Seon-Kyoo Lee; Young-Sang Kim; Hong-June Park; Jae-Yoon Sim (J. Electr. Comput. Eng., 2011)

A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface. - Hyung-Joon Chi; Jae-Seung Lee; Seong-Hwan Jeon; Seung-Jun Bae; Young-Soo Sohn; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2011)

A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL. - Young-Sang Kim; Seon-Kyoo Lee; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2011)

A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface. - Seon-Kyoo Lee; Seung-Jin Park; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2011)

A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL. - Hyung-Joon Chi; Young-Ho Choi; Soo-Min Lee; Jae-Yoon Sim; Hong-June Park; Jong-Jin Lim; Pil-Sung Kang; Bu-Yeol Lee; Jin-Cheol Hong; Hee-Sub Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump. - Jong-Hoon Kim; Jung-Bum Shin; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS. - Young Hun Seo; Seon-Kyoo Lee; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling. - Hyunsoo Ha; Yunjae Suh; Seon-Kyoo Lee; Hong-June Park; Jae-Yoon Sim (CICC, 2012)

A fractional-N frequency divider for SSCG using a single dual-modulus integer divider and a phase interpolator. - Young-Ho Choi; Jae-Yoon Sim; Hong-June Park (ISOCC, 2012)

An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits. - Il-Min Yi; Seung-Jun Bae; Young-Soo Sohn; Jae-Yoon Sim; Hong-June Park (ISOCC, 2012)

An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface. - Young-Sik Kim; Seon-Kyoo Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Bae Lee; Joo-Sun Choi; Hong-June Park; Jae-Yoon Sim (ISSCC, 2012)

A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation. - Seon-Kyoo Lee; Hyunsoo Ha; Hong-June Park; Jae-Yoon Sim (ISSCC, 2012)

Clock/Frequency Generation Circuits and Systems. - Woogeun Rhee; Antonio Liscidini; Jae-Yoon Sim; Kenichi Okada 001; Sudhakar Pamarti (J. Electr. Comput. Eng., 2012)

A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC. - Dong-Woo Jee; Young Hun Seo; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2012)

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines. - Hae-Kang Jung; Il-Min Yi; Soo-Min Lee; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2012)

A 1.25 ps Resolution 8b Cyclic TDC in 0.13 µm CMOS. - Young Hun Seo; Jun-Seok Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2012)

A 1.9-GHz Fractional-N Digital PLL With Subexponent ΔΣ TDC and IIR-Based Noise Cancellation. - Dong-Woo Jee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

45pW ESD clamp circuit for ultra-low power applications. - Yen-Po Chen; Yoonmyung Lee; Jae-Yoon Sim; Massimo Alioto; David T. Blaauw; Dennis Sylvester (CICC, 2013)

65nW CMOS temperature sensor for ultra-low power microsystems. - Seokhyeon Jeong; Jae-Yoon Sim; David T. Blaauw; Dennis Sylvester (CICC, 2013)

A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms. - Dong-Woo Jee; Dennis Sylvester; David T. Blaauw; Jae-Yoon Sim (ISSCC, 2013)

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX. - Soo-Min Lee; Jong-Hoon Kim; Jong-Sam Kim; Yunsaing Kim; Hyunbae Lee; Jae-Yoon Sim; Hong-June Park (ISSCC, 2013)

A 95fJ/b current-mode transceiver for 10mm on-chip interconnect. - Seon-Kyoo Lee; Seung-Hun Lee; Dennis Sylvester; David T. Blaauw; Jae-Yoon Sim (ISSCC, 2013)

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL. - Dong-Woo Jee; Yunjae Suh; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2013)

A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS. - Jun-Seok Kim; Young Hun Seo; Yunjae Suh; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2013)

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation. - Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2013)

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface. - Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier. - Yunjae Suh; Jongmi Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits. - Ji-Yong Um; Yoon-Jee Kim; Eun-Woo Song; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Circuit techniques for miniaturized biomedical sensors. - Inhee Lee 001; Yejoong Kim; Suyoung Bang; Gyouho Kim; Hyunsoo Ha; Yen-Po Chen; Dongsuk Jeon; Seokhyun Jeong; Wanyeong Jung; Mohammad Hassan Ghaed; Zhiyoong Foo; Yoonmyung Lee; et al. (CICC, 2014)

A voltage-scalable 10-b pipelined ADC with current-mode amplifier. - Yunjae Suh; Seungnam Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (CICC, 2014)

A 0.4 V driving multi-touch capacitive sensor with the driving signal frequency set to (n+0.5) times the inverse of the LCD VCOM noise period. - Jae-Seung Lee; Dong-Hee Yeo; Sang-Soo Lee; Hye-Jung Kwon; Jae-Yoon Sim; Byungsub Kim; Hong-June Park (ISCAS, 2014)

2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface. - Dong Hoon Baek; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2014)

12.6 A 160nW 63.9fJ/conversion-step capacitance-to-digital converter for ultra-low-power wireless sensor nodes. - Hyunsoo Ha; Dennis Sylvester; David T. Blaauw; Jae-Yoon Sim (ISSCC, 2014)

2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology. - Seungho Han; Sooeun Lee; Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (ISSCC, 2014)

24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area. - Ji-Yong Um; Eun-Woo Song; Yoon-Jee Kim; Seong-Eun Cho; Min-Kyun Chae; Jongkeun Song; Bae-Hyung Kim; Seunghun Lee; Jihoon Bang; Youngil Kim; Kyungil Cho; Byungsub Kim; et al. (ISSCC, 2014)

A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes. - Seokhyeon Jeong; Zhiyoong Foo; Yoonmyung Lee; Jae-Yoon Sim; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2014)

Current-Mode Transceiver for Silicon Interposer Channel. - Seung-Hun Lee; Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2014)

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface. - Soo-Min Lee; Il-Min Yi; Hae-Kang Jung; Hyunbae Lee; Yong-Ju Kim; Yunsaing Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2014)

An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array. - Ji-Yong Um; Yoon-Jee Kim; Seong-Eun Cho; Min-Kyun Chae; Jongkeun Song; Bae-Hyung Kim; Seung-Hun Lee; Jihoon Bang; Youngil Kim; Kyungil Cho; Byungsub Kim; Jae-Yoon Sim; et al. (IEEE Trans. Biomed. Circuits Syst., 2014)

An Approximate Closed-Form Channel Model for Diverse Interconnect Applications. - Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation. - Hyunsoo Ha; Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current. - Hye-Jung Kwon; Jae-Seung Lee; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS. - Kyongsu Lee; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2014)

An ultra-low-power biomedical chip for injectable pressure monitor. - Inhee Lee 001; Wanyeong Jung; Hyunsoo Ha; Seokhyeon Jeong; Yejoong Kim; Gyouho Kim; Zhiyoong Foo; Jae-Yoon Sim; Dennis Sylvester; David T. Blaauw (BioCAS, 2015)

A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design. - Sooeun Lee; Gunbok Lee; Jae-Yoon Sim; Hong-June Park; Wee Sang Park; Byungsub Kim (ICCAD, 2015)

5.7 A 29nW bandgap reference circuit. - Jongmi Lee; Youngwoo Ji; Seungnam Choi; Young-Chul Cho; Seong-Jin Jang; Joo-Sun Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2015)

Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform. - Dong-Woo Jee; Dennis Sylvester; David T. Blaauw; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2015)

A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer. - Ji-Yong Um; Yoon-Jee Kim; Seong-Eun Cho; Min-Kyun Chae; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Biomed. Circuits Syst., 2015)

An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects. - Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A low-power LDO circuit with a fast load regulation. - Young Jae Jang; Seong-Eun Cho; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (APCCAS, 2016)

All-synthesizable 6Gbps voltage-mode transmitter for serial link. - Young-Ho Choi; Kihwan Seong; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (A-SSCC, 2016)

All-synthesizable transmitter driver and data recovery circuit for USB2.0 interface. - Kihwan Seong; Won-Cheol Lee; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (ISOCC, 2016)

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. - Il-Min Yi; Seung-Jun Bae; Min-Kyun Chae; Soo-Min Lee; Young Jae Jang; Young-Chul Cho; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (VLSI Circuits, 2016)

A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC. - Dong-Woo Jee; Yunjae Suh; Hong-June Park; Jae-Yoon Sim (J. Circuits Syst. Comput., 2016)

A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement. - Seungho Han; Sooeun Lee; Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE J. Solid State Circuits, 2016)

A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC. - Shinwoong Kim; Seunghwan Hong; Kapseok Chang; Hyungsik Ju; Jaewook Shin; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2016)

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface. - Soo-Min Lee; Ji-Hoon Lim; Il-Min Yi; Young Jae Jang; Hae-Kang Jung; Kyunghoon Kim; Dae-Han Kwon; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2016)

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization. - Seungnam Choi; Hyunwoo Son; Jongshin Shin; Sang-Hyun Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling. - Kyongsu Lee; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs. - Ji-Hoon Lim; Jun-Hyun Bae; Jaemin Jang; Hae-Kang Jung; Hyunbae Lee; Yongju Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A Low-Power Class-AB Gm-Based Amplifier With Application to an 11-bit Pipelined ADC. - Yunjae Suh; Seungnam Choi; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links. - Myungguk Lee; Seungho Han; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (A-SSCC, 2017)

8.7 A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz. - Hwasuk Cho; Kihwan Seong; Kwang-Hee Choi; Jin-Hyeok Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2017)

5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit. - Youngwoo Ji; Cheonhoo Jeon; Hyunwoo Son; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2017)

5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop. - Jahyun Koo 001; Kyoung-Sik Moon; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2017)

23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS. - Il-Min Yi; Min-Kyun Chae; Seok-Hun Hyun; Seung-Jun Bae; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (ISSCC, 2017)

A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation. - Yoon-Jee Kim; Sung-Eun Cho; Ji-Yong Um; Min-Kyun Chae; Jihoon Bang; Jongkeun Song; Taeho Jeon; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Biomed. Circuits Syst., 2017)

A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors. - Hyunwoo Son; Hwasuk Cho; Jahyun Koo 001; Youngwoo Ji; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2017)

A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop. - Young-Ho Choi; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC. - Seungnam Choi; Yunjae Suh; Joohyun Lee; Jinkyu Kim; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications. - Seunghwan Hong; Shinwoong Kim; Seungnam Choi; Hwasuk Cho; Jaehyeong Hong; Young Hun Seo; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

An Approximate Transfer Function Model of Two Serially Connected Heterogeneous Transmission Lines. - Jaeyoung Seo; Minsoo Choi 002; Sanquan Song; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface. - Kihwan Seong; Won-Cheol Lee; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Investigation on the Worst Read Scenario of a ReRAM Crossbar Array. - Yelim Youn; Kwangmin Kim; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic. - Youngwoo Ji; Cheonhoo Jeon; Hyunwoo Son; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ASP-DAC, 2018)

A 16.6-pJ/b 150-Mb/s body-channel communication transceiver with decision feedback equalization improving >200x area efficiency. - Ji-Hoon Lee; Kwangmin Kim; Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (ASP-DAC, 2018)

A low-power wide dynamic-range current readout circuit for biosensors. - Hyunwoo Son; Hwasuk Cho; Jahyun Koo 001; Youngwoo Ji; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ASP-DAC, 2018)

A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC. - Minseob Lee; Shinwoong Kim; Hwasuk Cho; Jahyun Koo 001; Kwang-Hee Choi; Jin-Hyeok Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2018)

A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces. - Sooeun Lee; Jaeyoung Seo; Kyunghyun Lim; Jaehyun Ko 001; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (ISSCC, 2018)

An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications. - Seungnam Choi; Hwan-Seok Ku; Hyunwoo Son; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2018)

An FFE Transmitter Which Automatically and Adaptively Relaxes Impedance Matching. - Minsoo Choi 002; Sooeun Lee; Myungguk Lee; Ji-Hoon Lee; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE J. Solid State Circuits, 2018)

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface. - Il-Min Yi; Min-Kyun Chae; Seok-Hun Hyun; Seung-Jun Bae; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2018)

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table. - Hwasuk Cho; Hyunwoo Son; Kihwan Seong; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2018)

A Study on Bandgap Reference Circuit With Leakage-Based PTAT Generation. - Youngwoo Ji; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Search Algorithm for the Worst Operation Scenario of a Cross-Point Phase-Change Memory Utilizing Particle Swarm Optimization. - Kwangmin Kim; Seokjoon Kang; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect. - Youngwoo Ji; Jungho Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2019)

A 143nW Glucose-Monitoring Smart Contact Lens IC with a Dual-Mode Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission Using a Single Loop Antenna. - Cheonhoo Jeon; Jahyun Koo 001; Kyongsu Lee; Su-Kyoung Kim; Sei Kwang Hahn; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (VLSI Circuits, 2019)

A 2.5Gbps Transceiver and Channel Architecture for High-Speed Automotive Communication System. - Kyongsu Lee; Jae-Yoon Sim (IEICE Trans. Electron., 2019)

A 192-pW Voltage Reference Generating Bandgap- $V_{ text{th}}$ With Process and Temperature Dependence Compensation. - Youngwoo Ji; Jungho Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2019)

A 0.0043-mm2 0.3-1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC. - Minseob Lee; Shinwoong Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2019)

Introduction to the Special Section on the 2018 Asian Solid-State Circuits Conference (A-SSCC). - Hong-June Park; Jae-Yoon Sim; Robert Chen-Hao Chang (IEEE J. Solid State Circuits, 2019)

A Multilayer-Learning Current-Mode Neuromorphic System With Analog-Error Compensation. - Hyunwoo Son; Hwasuk Cho; Jungho Lee; Seongun Bae; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2019)

A Quadrature RC Oscillator With Noise Reduction by Voltage Swing Control. - Jahyun Koo 001; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

High-speed transceiver network for in-vehicle communication system. - Kyongsu Lee; Jae-Yoon Sim (ISOCC, 2020)

A Body Channel Communication Technique Utilizing Decision Feedback Equalization. - Ji-Hoon Lee; Jaehyun Ko 001; Kwangmin Kim; Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Access, 2020)

A Smart Contact Lens Controller IC Supporting Dual-Mode Telemetry With Wireless-Powered Backscattering LSK and EM-Radiated RF Transmission Using a Single-Loop Antenna. - Cheonhoo Jeon; Jahyun Koo 001; Kyongsu Lee; Minseob Lee; Su-Kyoung Kim; Sangbaie Shin; Sei Kwang Hahn; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2020)

A pattern-dependent injection-locked CDR for clock-embedded signaling. - Jaehyeong Hong; Dong Hoon Baek; Hyunwoo Son; Cheolmin Ahn; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (Microelectron. J., 2020)

An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss. - Cheolmin Ahn; Jaehyeong Hong; Jongshin Shin; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst., 2020)

Low-Power Small-Area Inverter-Based DSM for MEMS Microphone. - Seong-Eun Cho; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst., 2020)

A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects. - Sooeun Lee; Jaeyoung Seo; Kyunghyun Lim; Jahyun Koo 001; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Picosecond-Resolution Digitally-Controlled Timing Generator With One-Clock-Latency at Arbitrary Instantaneous Input. - Jaehan Park; Cheolmin Ahn; Jaehyeong Hong; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 490-pW SAR Temperature Sensor With a Leakage-Based Bandgap-Vth Reference. - Bumjin Park; Youngwoo Ji; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels. - Jaeyoung Seo; Jaehyun Ko 001; Kyunghyun Lim; Sooeun Lee; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Physically Unclonable Function Combining a Process Mismatch Amplifier in an Oscillator Collapse Topology. - Jaehan Park; Jae-Yoon Sim (ISSCC, 2021)

A 5.5mW/Channel 2-to-7 GHz Frequency Synthesizable Qubit-Controlling Cryogenic Pulse Modulator for Scalable Quantum Computers. - Kiseo Kang; ByungJun Kim; Gahyun Choi; Sun-Kyung Lee 002; Jisoo Choi; Jaeho Lee; Seokhyeong Kang; Moonjoo Lee; Ho-Jin Song; Yonuk Chong; Jae-Yoon Sim (VLSI Circuits, 2021)

A 2.5-nW Radio Platform With an Internal Wake-Up Receiver for Smart Contact Lens Using a Single Loop Antenna. - Cheonhoo Jeon; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2021)

A 26GHz Fractional-N Digital Frequency Synthesizer Leveraging Noise Profiles of Three Functional Stages. - Seongun Bae; Minseob Lee; Hwasuk Cho; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces. - Sooeun Lee; Jaeyoung Seo; Changyoon Han; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers. - Sunghye Park; Daeyeon Kim; Minhyuk Kweon; Jae-Yoon Sim; Seokhyeong Kang (DAC, 2022)

Configurable Energy-Efficient Lattice-Based Post-Quantum Cryptography Processor for IoT Devices. - ByungJun Kim; Jaehan Park; Seunghyun Moon; Kiseo Kang; Jae-Yoon Sim (ESSCIRC, 2022)

MCQA: Multi-Constraint Qubit Allocation for Near-FTQC Device. - Sunghye Park; Dohun Kim; Jae-Yoon Sim; Seokhyeong Kang (ICCAD, 2022)

A Time-Division Multiplexed 8-Channel Non-Contact ECG Recording IC with a Common-Mode Interference Tolerance of 20VPP. - Kyu-Jin Choi; Jae-Yoon Sim (ISSCC, 2022)

A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving 7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature Range. - Youngwoo Ji; Jiawei Liao; Sina Arjmandpour; Alessandro Novello; Jae-Yoon Sim; Taekwang Jang (ISSCC, 2022)

A Cryo-CMOS Controller IC With Fully Integrated Frequency Generators for Superconducting Qubits. - Kiseo Kang; Donggyu Minn; Seunghun Bae; Jaeho Lee; Seongun Bae; Gichang Jung; Seokhyeong Kang; Moonjoo Lee; Ho-Jin Song; Jae-Yoon Sim (ISSCC, 2022)

13-K Tnoise Cryo-CMOS Parametric Amplifier at 80 mK for Quantum Computers. - Goeun Baek; Seunghun Bae; Minki Lee; Hyuncheol Park; Kangseop Lee; Jae-Yoon Sim; Moonjoo Lee; Ho-Jin Song (VLSI Technology and Circuits, 2022)

A 40-nm Cryo-CMOS Quantum Controller IC for Superconducting Qubit. - Kiseo Kang; Donggyu Minn; Seongun Bae; Jaeho Lee; Seokhyeong Kang; Moonjoo Lee; Ho-Jin Song; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2022)

A BER-Suppressed PUF With an Amplification of Process Mismatch Effect in an Oscillator Collapse Topology. - Jaehan Park; ByungJun Kim; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2022)

A 12μs-Conversion, 20mK-Resolution Temperature Sensor Based on SAR ADC. - Hwan-Seok Ku; Seungnam Choi; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 384G Output NonZeros/J Graph Convolutional Neural Network Accelerator. - Kyeong-Jun Lee; Seunghyun Moon; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An 8.9-71.3 TOPS/W Deep Learning Accelerator for Arbitrarily Quantized Neural Networks. - Seunghyun Moon; Kyeong-Jun Lee; Han-Gyeol Mun; Byungjun Kim; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A PVT-Tolerant Oscillation-Collapse-Based True Random Number Generator With an Odd Number of Inverter Stages. - Jaehan Park; Byungjun Kim; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An Auto-Configurable Dual-Mode MPPT for Energy Harvesting With 12 nW-180 mW Conversion Range. - Heesung Roh; Youngwoo Ji; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Performance Enhancement of Capacitive-Type Torque Sensor by Using Resonant Circuit. - Jaeyun Kim; Yong Bum Kim; Dong-Yeop Seok; Seung Yeon Lee; Jae-Yoon Sim; Hyouk Ryeol Choi (IEEE Trans. Ind. Electron., 2022)

A 20.5-nW Resistor-Less Bandgap Voltage Reference With Self-Biased Compensation for Process Variations. - Youngwoo Ji; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Low-Noise Distributed RC Oscillator. - Jahyun Koo 001; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2022)

An 18.6-$ mu $W/Ch TDM-Based 8-Channel Noncontact ECG Recording IC With Common-Mode Interference Suppression. - Kyu-Jin Choi; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2022)

A 7-10b Programmable Cryo-CMOS TI-SAR ADC for Multichannel Qubit Readout with On-Chip Background Inter-Channel Mismatch Calibrations. - Jaeho Lee; Kiseo Kang; Donggyu Minn; Jae-Yoon Sim (ESSCIRC, 2023)

Joint Optimization of Cache Management and Graph Reordering for GCN Acceleration. - Kyeong-Jun Lee; ByungJun Kim; Han-Gyeol Mun; Seunghyun Moon; Jae-Yoon Sim (ISLPED, 2023)

A Cryogenic Controller IC for Superconducting Qubits with DRAG Pulse Generation by Direct Synthesis without Using Memory. - Kiseo Kang; Donggyu Minn; Jaeho Lee; Ho-Jin Song; Moonjoo Lee; Jae-Yoon Sim (ISSCC, 2023)

A 127.8TOPS/W Arbitrarily Quantized 1-to-8b Scalable-Precision Accelerator for General-Purpose Deep Learning with Reduction of Storage, Logic and Latency Waste. - Seunghyun Moon; Han-Gyeol Mun; Hyunwoo Son; Jae-Yoon Sim (ISSCC, 2023)

A 110dB-TCMRR TDM-based 8-Channel Noncontact ECG Recording IC with Suppression of Motion-Induced Coupling in PP. - Kyu-Jin Choi; Seungnam Choi; Jae-Yoon Sim (VLSI Technology and Circuits, 2023)

A 28 nm 66.8 TOPS/W Sparsity-Aware Dynamic-Precision Deep-Learning Processor. - Han-Gyeol Mun; Hyunwoo Son; Seunghyun Moon; Jaehyun Park; ByungJun Kim; Jae-Yoon Sim (VLSI Technology and Circuits, 2023)

A 6.5nW, -73.5dBm Sensitivity, Cryptographic Wake-Up Receiver with a PUF-based OTP and Temperature-Insensitive Code Recovery. - Jaehan Park; Cheonhoo Jeon; Donggyu Minn; Heesung Roh; Jae-Yoon Sim (VLSI Technology and Circuits, 2023)

A Reconfigurable LDO-Assisted Physically Unclonable Function Achieving a Zero-BER With 14% Masking. - Jaehan Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Bottleneck-Stationary Compact Model Accelerator With Reduced Requirement on Memory Bandwidth for Edge Applications. - Han-Gyeol Mun; Seunghyun Moon; Byungjun Kim; Kyeong-Jun Lee; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Corrections to "Low-Noise Distributed RC Oscillator". - Jahyun Koo 001; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Temperature Compensated Ring Oscillator With LC-Based Period Error Detection. - Seongun Bae; Minseob Lee; Sang-Min Yoo; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Trans-Net: Knowledge-Transferring Analog Circuit Optimizer with a Netlist-Based Circuit Representation. - Ho-Jin Lee; Kyeong-Jun Lee; Youngchang Choi; Kyongsu Lee; Seokhyeong Kang; Jae-Yoon Sim (DATE, 2024)

A 246-fJ/b 13.3-Tb/s/mm Single-Ended Current-Mode Transceiver with Crosstalk Cancellation for Shield-Less Short-Reach Interconnect. - Jaeho Lee; Kyongsu Lee; Jae-Yoon Sim; Seon-Kyoo Lee (VLSI Technology and Circuits, 2024)

A $94 text{fs}_{ text{rms}}$-Jitter and -249.3dB FoM 4.0GHz Ring-Oscillator-Based MDLL with Background Calibration of Phase Offset and Injection Slope Mismatch. - Dongjun Park; Heesung Roh; Seon-Kyoo Lee; Jae-Yoon Sim (VLSI Technology and Circuits, 2024)

A Smart Contact Lens System with 433MHz Wireless Power and Data Transfer at a Modulation Index Down to 0.02%. - Heesung Roh; Hyun Jin Yoo; Si-Youl Yoo; Seung Hee Pyen; Cheonhoo Jeon; Jae-Yoon Sim (VLSI Technology and Circuits, 2024)

Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and Latency Waste. - Seunghyun Moon; Han-Gyeol Mun; Hyunwoo Son; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2024)

PC-Opt: Partition and Conquest-based Optimizer using Multi-Agents for Complex Analog Circuits. - Youngchang Choi; Sejin Park 001; Ho-Jin Lee; Kyongsu Lee; Jae-Yoon Sim; Seokhyeong Kang (ASP-DAC, 2025)

A 1.43-nW 1.3-kHz Resistor-Less Relaxation Oscillator With 67.3-ppm/ ° C Stability. - Jiho Lee; Jae-Yoon Sim (IEEE Access, 2025)

A 600-V Peak-to-Peak 65-dBc RF Signal Source for Trapped-Ion Quantum Computing. - Seongchan Bae; Myunghun Kim; Junhee Cho; Moonjoo Lee; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 9.6-nW Wake-Up Timer With RC-Referenced Subharmonic Locking Using Dual Leakage-Based Oscillators. - Jahyun Koo 001; Hyunwoo Son; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 40 nm Cryo-CMOS Homodyne-Demodulation Readout SoC for Superconducting Qubits. - Donggyu Minn; Kiseo Kang; Jaeho Lee; Seongchan Bae; Byungjun Kim; Jaehoon Lee; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Quantum Controller IC With DRAG Generation in 40-nm Cryo-CMOS for Scalable Superconducting Quantum Computing. - Kiseo Kang; Seongchan Bae; Donggyu Minn; Jaeho Lee; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2025)