Systematic Customization of On-Chip Crossbar Interconnects. - Jae Young Hur; Todor P. Stefanov; Stephan Wong; Stamatis Vassiliadis (ARC, 2007)

Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs. - Jae Young Hur; Stephan Wong; Stamatis Vassiliadis (ARC, 2007)

Customizing Reconfigurable On-Chip Crossbar Scheduler. - Jae Young Hur; Todor P. Stefanov; Stephan Wong; Stamatis Vassiliadis (ASAP, 2007)

Yeast on a Chip - Single-cell Analyses of MAPK Signaling Pathways in Saccharomyces Cerevisiae using Cell Chips. - Min Cheol Park; Moon Kyu Kwak; Hye Sung Cho; Kahp Y. Suh; Jae Young Hur; Sang-Hyun Park (BIODEVICES (2), 2008)

Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. - Kees Goossens; Martijn T. Bennebroek; Jae Young Hur; Muhammad Aqeel Wahlah (NOCS, 2008)

A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices. - Thomas Marconi; Jae Young Hur; Koen Bertels; Georgi Gaydadjiev (SASP, 2010)

Design Trade-offs in Customized On-chip Crossbar Schedulers. - Jae Young Hur; Stephan Wong; Todor P. Stefanov (J. Signal Process. Syst., 2010)

Customizing and hardwiring on-chip interconnects in FPGAs. - Jae Young Hur (2011)

Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays. - Jae Young Hur; Kees Goossens; Lotfi Mhamdi; Muhammad Aqeel Wahlah (IET Comput. Digit. Tech., 2012)

Customisation of on-chip network interconnects and experiments in field-programmable gate arrays. - Jae Young Hur; Todor P. Stefanov; Stephan Wong; Kees Goossens (IET Comput. Digit. Tech., 2012)

Representing Contiguity in Page Table for Memory Management Units. - Jae Young Hur (MCSoC, 2017)

Adaptive Linear Address Map for Bank Interleaving in DRAMs. - Jae Young Hur; Sang Woo Rhim; Beom Hak Lee; Wooyoung Jang (IEEE Access, 2019)

Block Level TLB Coalescing for Buddy Memory Allocator. - Jae Young Hur (IEICE Trans. Inf. Syst., 2019)

Contiguity Representation in Page Table for Memory Management Units. - Jae Young Hur (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Page Table Compaction for TLB Coalescing. - Jae Young Hur; Joonho Kong (IEEE Access, 2020)

Near-Threshold L1 Data Cache for Yield Management Under Process Variations. - Joonho Kong; Jae Young Hur (IEEE Access, 2020)

TLC STT-MRAM aware LLC for multicore processor. - Taejin Park; Jae Young Hur; Wooyoung Jang (IEICE Electron. Express, 2020)

Virtual Address Remapping with Configurable Tiles in Image Processing Applications. - Jae Young Hur (IEICE Trans. Inf. Syst., 2020)

Clean-prefetcher: look-ahead prefetching without cache pollution. - Minshin Cho; Jae Young Hur; Wooyoung Jang (IEICE Electron. Express, 2021)

Page-Size Aware Buddy Allocator With Unaligned Range Supports for TLB Coalescing. - Dai-Duong Tran; Jae Young Hur (IEEE Access, 2023)

TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices. - Dai-Duong Tran; Young Seung Kim; Jae Young Hur (IEEE Access, 2025)

Contiguity aware TLB prefetching for embedded I/O devices. - Dai-Duong Tran; Jae Young Hur (IEICE Electron. Express, 2025)