A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface. - Woo-Yeol Shin; Gi-Moon Hong; Hyongmin Lee; Jaeduk Han; Sunkwon Kim; Kyu-Sang Park; Dong-Hyuk Lim; Jung-Hoon Chun; Deog-Kyoon Jeong; Suhwan Kim 001 (ISSCC, 2011)

A 60Gb/s 173mW receiver frontend in 65nm CMOS technology. - Jaeduk Han; Yue Lu 007; Nicholas Sutardja; Kwangmo Jung; Elad Alon (VLSIC, 2015)

Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology. - Jaeduk Han; Yue Lu 007; Nicholas Sutardja; Kwangmo Jung; Elad Alon (IEEE J. Solid State Circuits, 2016)

A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET. - Angie Wang; Brian C. Richards; Daniel Palmer Dabbelt; Howard Mao; Stevo Bailey; Jaeduk Han; Eric Chang; James Dunn 003; Elad Alon; Borivoje Nikolic (A-SSCC, 2017)

Non-blind Image Deconvolution using Sampling without Replacement. - Jaeduk Han; Jonghyun Kim; Moon Gi Kang (Image Processing: Algorithms and Systems, 2017)

6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology. - Jaeduk Han; Yue Lu 007; Nicholas Sutardja; Elad Alon (ISSCC, 2017)

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (ISSCC, 2017)

Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology. - Jaeduk Han; Nicholas Sutardja; Yue Lu 007; Elad Alon (IEEE J. Solid State Circuits, 2017)

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (IEEE J. Solid State Circuits, 2017)

A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. - Stevo Bailey; Jaeduk Han; Paul Rigge; Richard Lin; Eric Chang; Howard Mao; Zhongkai Wang; Chick Markley; Adam M. Izraelevitz; Angie Wang; Nathan Narevsky; Woo-Rham Bae; et al. (A-SSCC, 2018)

BAG2: A process-portable framework for generator-based AMS circuit design. - Eric Chang; Jaeduk Han; Woo-Rham Bae; Zhongkai Wang; Nathan Narevsky; Borivoje Nikolic; Elad Alon (CICC, 2018)

A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. - Angie Wang; Woo-Rham Bae; Jaeduk Han; Stevo Bailey; Paul Rigge; Orhan Ocal; Zhongkai Wang; Kannan Ramchandran; Elad Alon; Borivoje Nikolic (ESSCIRC, 2018)

An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit. - Eric Chang; Nathan Narevsky; Jaeduk Han; Elad Alon (VLSI Circuits, 2018)

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Jaeduk Han; Deog-Kyoon Jeong (IEEE Trans. Ind. Electron., 2018)

Permuted Coordinate-Wise Optimizations Applied to Lp-Regularized Image Deconvolution. - Jaeduk Han; Ki-Sun Song; Jonghyun Kim; Moon Gi Kang (IEEE Trans. Image Process., 2018)

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET. - Jaeduk Han; Eric Chang; Stevo Bailey; Zhongkai Wang; Woo-Rham Bae; Angie Wang; Nathan Narevsky; Amy Whitcombe; Pengpeng Lu; Borivoje Nikolic; Elad Alon (CICC, 2019)

A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit. - Nicholas Sutardja; Jaeduk Han; Nathan Narevsky; Elad Alon (ESSCIRC, 2019)

Multi-frame super-resolution utilizing spatially adaptive regularization for ToF camera. - Haegeun Lee; Jonghyun Kim; Jaeduk Han; Moon Gi Kang (Image Processing: Algorithms and Systems, 2019)

Design and Automatic Generation of High-Speed Circuits for Wireline Communications. - Jaeduk Han; Eric Chang; Elad Alon (ISOCC, 2019)

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. - Steven Bailey; Paul Rigge; Jaeduk Han; Richard Lin; Eric Chang; Howard Mao; Zhongkai Wang; Chick Markley; Adam M. Izraelevitz; Angie Wang; Nathan Narevsky; Woo-Rham Bae; et al. (IEEE J. Solid State Circuits, 2019)

A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. - Angie Wang; Woo-Rham Bae; Jaeduk Han; Stevo Bailey; Orhan Ocal; Paul Rigge; Zhongkai Wang; Kannan Ramchandran; Elad Alon; Borivoje Nikolic (IEEE J. Solid State Circuits, 2019)

Computational Color Constancy under Multiple Light Sources. - Jaeduk Han; Soonyoung Hong; Moon Gi Kang (Image Processing: Algorithms and Systems, 2020)

Design Techniques for Robust and Area-efficient Current Sources in Nanometer CMOS Technology. - Taeung No; Jaeduk Han (ISOCC, 2020)

Multi-Frame Depth Super-Resolution for ToF Sensor With Total Variation Regularized L1 Function. - Jonghyun Kim; Jaeduk Han; Moon Gi Kang (IEEE Access, 2020)

Canonical Illumination Decomposition and Its Applications. - Jaeduk Han; Soonyoung Hong; Moon Gi Kang (IEEE Trans. Circuits Syst. Video Technol., 2020)

Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies. - Youngbog Yoon; Daeyong Han; Shinho Chu; Sangho Lee; Jaeduk Han; Junhyun Chun (DATE, 2021)

Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology. - Dongjun Lee; Jaeduk Han (ISOCC, 2021)

A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits. - Taeho Shin; Jaeduk Han (ISOCC, 2021)

High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology. - Gaeryun Sung; Jaeduk Han (ISOCC, 2021)

8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS. - Minsoo Choi 002; Zhongkai Wang; Kyoungtae Lee; Kwanseo Park; Zhaokai Liu; Ayan Biswas; Jaeduk Han; Elad Alon (ISSCC, 2021)

Thermal Image Restoration Based on LWIR Sensor Statistics. - Jaeduk Han; Haegeun Lee; Moon Gi Kang (Sensors, 2021)

Automatic prior selection for image deconvolution: Statistical modeling on natural images. - Haegeun Lee; Jaeduk Han; Soonyoung Hong; Moon Gi Kang (Signal Process., 2021)

LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies. - Jaeduk Han; Woo-Rham Bae; Eric Chang; Zhongkai Wang; Borivoje Nikolic; Elad Alon (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Energy-Efficient Bus Encoding Techniques for Next-Generation PAM-4 DRAM Interfaces. - Youri Su; Sanghun Lee; Eunji Song; Dongha Kim; Jaeduk Han; Hokeun Kim (ICCD, 2022)

A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow. - Zhongkai Wang; Minsoo Choi 002; John Charles Wright; Kyoungtae Lee; Zhaokai Liu; Bozhi Yin; Jaeduk Han; Sijun Du; Elad Alon (ISCAS, 2022)

A 32-Gb/s High-Swing PAM-4 Current-Mode Driver with Current-Bleeding Cascode Technique and Capacitive-Coupled Pre-drivers in 40-nm CMOS for Short-Reach Wireline Communications. - Eunji Song; Jeonghyu Yang; Seungwook Hong; Jaeduk Han (MWSCAS, 2022)

A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. - Zhongkai Wang; Minsoo Choi 002; Paul Kwon; Kyoungtae Lee; Bozhi Yin; Zhaokai Liu; Kwanseo Park; Ayan Biswas; Jaeduk Han; Sijun Du; Elad Alon (VLSI Technology and Circuits, 2022)

A Discharge-Path-Based Sensing Circuit With OTS Snapback Current Protection for Phase Change Memories. - Taeung No; Seonjun Choi; Gaeryun Sung; Seong-Beom Kim; Jaeduk Han; Yun Heub Song (IEEE Access, 2022)

A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids. - Taeho Shin; Dongjun Lee; Dongwhee Kim; Gaeryun Sung; Wookjin Shin; Yunseong Jo; Hyungjoo Park; Jaeduk Han (CoRR, 2022)

An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS. - Zhongkai Wang; Minsoo Choi 002; Kyoungtae Lee; Kwanseo Park; Zhaokai Liu; Ayan Biswas; Jaeduk Han; Sijun Du; Elad Alon (IEEE J. Solid State Circuits, 2022)

A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS. - Eunsang Lee; Changhyun Pyo; Sanghun Lee; Jaeduk Han (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Analysis of CMOS Latched Comparators. - Sun-Ho Yeom; Taeyang Sim; Jaeduk Han (ICEIC, 2023)

Multi-Phase Frequency Divider Generator with Process-Independent Automation. - Jihoon Jang; Heedo Jeong; Jaeduk Han (ISOCC, 2023)

An Analysis of Current-mode Drivers in 40-nm CMOS Technology. - Bona Lim; Hanhee Jo; Jaeduk Han (ISOCC, 2023)

Analysis of Grounded Coplanar Waveguide (GCPW) for High-Speed Links Channel. - Youngmin Oh; Taeyang Sim; Jaeduk Han (ISOCC, 2023)

A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm. - Jeonghyu Yang; Eunji Song; Seungwook Hong; Dongjun Lee; Sangwan Lee; Hyunwoo Im; Taeho Shin; Jaeduk Han (ISSCC, 2023)

An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies. - Dongjun Lee; Gijin Park; Jaeduk Han; Min-Seong Choo (IEEE Access, 2023)

A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend. - Hyeongmin Seo; Jiyun Han; Kyungmin Kim 003; Baek-Jin Lim; EunSeok Shin; Youngdon Choi; Hyungjong Ko; Jung-Hwan Choi; Sang-Hyun Lee; Changsik Yoo; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS. - Hyuntae Kim; Hyeongmin Seo; Yunseong Jo; Changsik Yoo; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS. - Hyochang Kim; Hyeongmin Seo; Hyuntae Kim; Changsik Yoo; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers. - Kunmo Kim; Suhong Moon; Jaeduk Han; Elad Alon; Ali M. Niknejad (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies. - Taeho Shin; Dongjun Lee; Dongwhee Kim; Gaeryun Sung; Wookjin Shin; Yunseong Jo; Hyungjoo Park; Jaeduk Han (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Non-parametric Sensor Noise Modeling and Synthesis. - Ali Mosleh; Luxi Zhao 002; Atin Singh; Jaeduk Han; Abhijith Punnappurath; Marcus A. Brubaker; Jihwan Choe; Michael S. Brown (ECCV (24), 2024)

A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS. - Zhongkai Wang; Minsoo Choi 002; Paul Kwon; Zhaokai Liu; Bozhi Yin; Kyoungtae Lee; Kwanseo Park; Ayan Biswas; Jaeduk Han; Sijun Du; Elad Alon (ISCAS, 2024)

Analysis of Test Environment Configuration for High-Speed Link Chip Measurement. - Yunseong Jo; Hyuntae Kim; Jaeduk Han (ISOCC, 2024)

Low-Power Encoding for PAM-3 DRAM Bus. - Jonghyeon Nam; Jaeduk Han; Hokeun Kim (SMACD, 2024)

Analog Circuit Design Automation via Sequential RL Agents and Gm/ID Methodology. - Sungweon Hong; Yunseob Tae; Dongjun Lee; Gijin Park; Jaemyung Lim; Kyungjun Cho; Chunseok Jeong; Myeong-Jae Park; Songnam Hong 001; Jaeduk Han (IEEE Access, 2024)

Interactive and Automatic Generation of Primitive Custom Circuit Layout Using LLMs. - Geunyoung You; Youjin Byun; Sojin Lim; Jaeduk Han (CoRR, 2024)

A 35-Gb/s PAM-4 Transmitter With 7B4Q Full-Transition Avoidance and Area-Efficient Gm-Boosting Techniques. - Eunji Song; Jiyun Han; Hyeongmin Seo; Hyuntae Kim; Hyunwoo Im; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology. - Taeyang Sim; Sun-Ho Yeom; Hyunwoo Im; Youngmin Oh; Hyeongmin Seo; Hyeongjun Ko; Hankyu Chi; Hae-Kang Jung; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS. - Wookjin Shin; Hyeongmin Seo; Sangwan Lee; Dong-Ho Choi; Young-Ho Kwak; Soon-Jae Won; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A PSRR-Enhanced Fast-Response Inverter-Based LDO for Mobile Devices. - Sanghun Lee; Jaemyung Lim; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology. - Youngmin Oh; Hyunwoo Im; Jeonghyu Yang; Eunji Song; Dongjun Lee; Sangwan Lee; Taeho Shin; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction. - Gijin Park; Sun-Ho Yeom; InWoo Jang; Dongjun Lee; Jaeduk Han; Min-Seong Choo (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces. - Hyuntae Kim; Yunseong Jo; Sanghun Lee; Eunsang Lee; Young Choi; Jaewoo Park; Myoungbo Kwak; Jung-Hwan Choi; Youngdon Choi; Jaeduk Han (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend With Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS. - Sangwan Lee; Hyeongmin Seo; Seungwoo Son; Sunoh Yeom; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology. - Yunseong Jo; Taeseung Kang; Jeonghyu Yang; Jaeduk Han (ASP-DAC, 2025)

A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-Tees. - Yooseong Jang; Seokmin Yun; Jeonghyu Yang; Taeho Shin; Eunji Song; Jaeduk Han (ISCAS, 2025)

A 96-Gb/s PAM-8 Transmitter with Transition-Boosted Current-Mode Logic Driver in 40-nm CMOS for Wireline Communication. - Bona Lim; Hanhee Jo; Heedo Jeong; Jeonghyu Yang; Jaeduk Han (ISCAS, 2025)

22.4 A 32-to-50Gb/s/pin Single-Ended PAM-4 Transmitter with a ZQ-Based FFE and PAM-4 LSB DBI-DC Encoding. - Yunseong Jo; Hyuntae Kim; Young Choi; Jaewoo Park; Myoungbo Kwak; Jaeduk Han (ISSCC, 2025)

Process-Portable Layout Generation of High-Speed Digital Circuit Using Standard Cells in FinFET. - Taeseung Kang; Taeho Shin; Heejun Kim; Jaeduk Han (SMACD, 2025)

WDP: A Weighted Delay Prediction Method for Integrated Circuit Interconnects. - Yoonsoo Park; Songnam Hong 001; Jaeduk Han (SMACD, 2025)

100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology. - Eunji Song; Jeonghyu Yang; Youngmin Oh; Seungwook Hong; Dongjun Lee; Sangwan Lee; Hyunwoo Im; Taeho Shin; Jaeduk Han (IEEE J. Solid State Circuits, 2025)

A Variation-Robust 20-Gb/s Wireline Transceiver With Real-Time Calibration in 28-nm CMOS. - Sangwan Lee; Hyeongmin Seo; Wookjin Shin; Dongju Yang; Gaeryun Sung; Sanghun Lee; Dong-Ho Choi; Young-Ho Kwak; Soon-Jae Won; Ickhyun Song; Jaeduk Han (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Flying-Capacitor-Assisted Single-Mode Buck-Boost Converter for Battery-Powered Applications. - Sunghae Kim; Taehee Lee; Kunhee Cho; Jaeduk Han (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 96-Gb/s 1.6-Vppd PAM-8 Transmitter With High-Swing and Low-Loading Cascaded Driver in 40-nm CMOS Technology. - Taeseung Kang; Jeonghyu Yang; Eunji Song; Seungwoo Son; Hyuntae Kim; Jaeduk Han (IEEE Trans. Very Large Scale Integr. Syst., 2025)