A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process. - Jaehun Jun; Jaegeun Song; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique. - Soonsung Ahn; Jaegeun Song; Chaegang Lim; Yohan Choi; Sooho Park; Yunsoo Park; Chulwoo Kim (ISOCC, 2020)

An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier. - Yunsoo Park; Jaegeun Song; Yohan Choi; Chaegang Lim; Soonsung Ahn; Chulwoo Kim (IEEE J. Solid State Circuits, 2020)

A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique. - Jaegeun Song; Jaehun Jun; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs. - Chaegang Lim; Yohan Choi; Yunsoo Park; Jaegeun Song; Soonsung Ahn; Sooho Park; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Home IoT device management blockchain platform using smart contracts and a countermeasure against 51% attacks. - Ho-Se Moon; Jaegeun Song; Hyeonwoo Shin; Juwook Jang (APIT, 2022)

An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter. - Chaegang Lim; Yohan Choi; Jaegeun Song; Soonsung Ahn; Seokwon Jang; Chulwoo Kim (IEEE J. Solid State Circuits, 2022)

A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique. - Jaegeun Song; Yunsoo Park; Chaegang Lim; Yohan Choi; Soonsung Ahn; Sooho Park; Chulwoo Kim (IEEE J. Solid State Circuits, 2022)

A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. - Kwanyeob Chae; Jiyeon Park; Jaegeun Song; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Taekyung Yeo; Kyeongkeun Kang; Sangsoo Park; Eunsu Kim; et al. (ISSCC, 2023)

A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM. - Yoonjae Choi; Jaegeun Song; Daero Kim; Myunggon Kim; Jiyeon Park; Jinho Choi; Changki Kwon; Minho Seo; Jihun Oh; Shinyoung Yi 002; Billy Koo; Kwanyeob Chae; et al. (A-SSCC, 2024)

A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. - Kwanyeob Chae; Jaegeun Song; Yoonjae Choi; Jiyeon Park; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Kyeongkeun Kang; Eunsu Kim; Juyoung Kim; et al. (IEEE J. Solid State Circuits, 2024)