A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS. - Jongmi Lee; Jongwoo Lee; Chilun Lo; Jaehoon Lee 005; In-Young Lee; Byungki Han; Seunghyun Oh; Thomas Byunghak Cho (A-SSCC, 2017)

A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS. - Barosaim Sung; Chilun Lo; Jaehoon Lee 005; Sangdon Jung; Seungjin Kim; Jaehong Jung; Seungyong Bae; Youngsea Cho; Yong Lim; Dooseok Choi; Myeongcheol Shin; Soonwoo Choi; et al. (A-SSCC, 2019)

An Effective Transconductance Controlled Offset Calibration for Dynamic Comparators. - Jaehoon Lee 005; Yong Lim; Barosaim Sung; Seunghyun Oh; Jung-Hoon Chun; Jongwoo Lee (ISCAS, 2020)

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product. - Sukhan Lee 002; Shinhaeng Kang; Jaehoon Lee 005; Hyeonsu Kim; Eojin Lee; Seungwoo Seo; Hosang Yoon; Seungwon Lee; Kyounghwan Lim; Hyunsung Shin; Jinhyun Kim; Seongil O; et al. (ISCA, 2021)

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications. - Young-Cheon Kwon; Sukhan Lee 002; Jaehoon Lee 005; Sang-Hyuk Kwon; Je-Min Ryu; Jong-Pil Son; Seongil O; Hak-soo Yu; Haesuk Lee; Soo Young Kim; Youngmin Cho; Jin Guk Kim; et al. (ISSCC, 2021)

6.1 A Low-Power and Low-Cost 14nm FinFET RFIC Supporting Legacy Cellular and 5G FR1. - Jongsoo Lee; Byoungjoong Kang; Seongwon Joo; Seokwon Lee; Joongho Lee; Seunghoon Kang; Ikkyun Jo; Suseop Ahn; Jaeseung Lee; Jeongyeol Bae; Won Ko; Woniun Jung; et al. (ISSCC, 2021)

10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter. - Chilun Lo; Jongmi Lee; Yong Lim; Younghyun Yoon; Hyunseok Hwang; Jaehoon Lee 005; Moo-Yeol Choi; Myungjin Lee; Seunghyun Oh; Jongwoo Lee (ISSCC, 2021)

A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration. - Jaehong Jung; Seunghyun Oh; Joo-Myoung Kim; Gihyeok Ha; Jinhyeon Lee; Seungjin Kim; Euiyoung Park; Jaehoon Lee 005; Yelim Yoon; Seungyong Bae; Wonkang Kim; Yong Lim; et al. (ISSCC, 2022)

A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET. - Barosaim Sung; Hyun-Gi Seok; Jaekwon Kim; Jaehoon Lee 005; Taejin Jang; Ilhoon Jang; Youngmin Kim; Anna Yu; Jong-Hyun Jang; Jiyoung Lee; Jeongyeol Bae; Euiyoung Park; et al. (ISSCC, 2022)

A 0.56mW 63.6dB SNDR 250MS/s SAR ADC in 8nm FinFET. - Jaehoon Lee 005; Yong Lim; Jongmi Lee; Taejin Jang; Kwonwoo Kang; Jongpil Cho; Seunghyun Oh; Jongwoo Lee (VLSI Technology and Circuits, 2022)

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Young-Cheon Kwon; Jaehoon Lee 005; Sung-Gi Ahn; Jaewon Park; Kijun Lee; Yu Ho Choi; Han-Won Cho; Jae San Kim; Jungyu Lee 002; Haesuk Lee; Seung Ho Song; et al. (VLSI Technology and Circuits, 2022)

A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET. - Barosaim Sung; Hyun-Gi Seok; Jaekwon Kim; Jaehoon Lee 005; Taejin Jang; Ilhoon Jang; Youngmin Kim; Anna Yu; Jong-Hyun Jang; Jiyoung Lee; Jeongyeol Bae; Euiyoung Park; et al. (IEEE J. Solid State Circuits, 2022)

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Sung-Gi Ahn; Jaehoon Lee 005; Jaewon Park; Yong-Ki Kim; Hyochang Kim; Yeong Geol Song; Han-Won Cho; Sunghye Cho; Seung Ho Song; Haesuk Lee; Useung Shin; et al. (IEEE J. Solid State Circuits, 2023)

A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module. - Joomyoung Kim; Jaehong Jung; Kwangmin Lim; Barosaim Sung; Jaekwon Kim; Baekmin Lim; Tae-Gun Noh; Jaehoon Lee 005; Hyun-Gi Seok; Youngsea Cho; Gyusik Kim; Takahiro Nomiyama; et al. (A-SSCC, 2024)

9.6 A 6th-Order Quadrature CTDSM using Double-OTA and Quadrature NSSAR with 171.3dB FoMs in 14nm. - Jongmi Lee; Seong-Eun Cho; Jaehoon Lee 005; Yong Lim; Seunghyun Oh; Jongwoo Lee; Sung-Ung Kwak (ISSCC, 2024)

9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm. - Yong Lim; Jaehoon Lee 005; Jongmi Lee; Kwangmin Lim; Seunghyun Oh; Jongwoo Lee; Sung-Ung Kwak (ISSCC, 2024)

A Fully Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS. - Jaehong Jung; Seunghyun Oh; Joomyoung Kim; Jinhyeon Lee; Wonkang Kim; Euiyoung Park; Seungyong Bae; Seungjin Kim; Jaehoon Lee 005; Yelim Youn; Yeongcheol Jeong; Sungsik Park; et al. (IEEE J. Solid State Circuits, 2024)

A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm. - Yong Lim; Jaehoon Lee 005; Jongmi Lee; Kwangmin Lim; Seunghyun Oh; Jongwoo Lee (IEEE J. Solid State Circuits, 2024)