A Simple Wrapped Core Linking Module for SoC Test Access. - Jaehoon Song; Sungju Park (Asian Test Symposium, 2002)

Hybrid test data compression technique for SOC scan testing. - Sangwook Cho; Jaehoon Song; Hyunbean Yi; Sungju Park (SoCC, 2005)

Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains. - Hyunbean Yi; Jaehoon Song; Sungju Park (ITC, 2006)

Efficient Interconnect Test Patterns for Crosstalk and Static Faults. - Pyoungwoo Min; Hyunbean Yi; Jaehoon Song; Sanghyeon Baeg; Sungju Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips. - Jaehoon Song; Hyunbean Yi; Juhee Han; Sungju Park (Asia-Pacific Computer Systems Architecture Conference, 2007)

Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC. - Jaehoon Song; Juhee Han; Dooyoung Kim; Hyunbean Yi; Sungju Park (ATS, 2007)

Design of Test Access Mechanism for AMBA-Based System-on-a-Chip. - Jaehoon Song; Piljae Min; Hyunbean Yi; Sungju Park (VTS, 2007)

An Efficient Secure Scan Design for an SoC Embedding AES Core. - Jaehoon Song; Taejin Jung; Junseop Lee; Hyeran Jeong; Byeongjin Kim; Sungju Park (ITC, 2008)

Low-Cost Scan Test for IEEE-1500-Based SoC. - Hyunbean Yi; Jaehoon Song; Sungju Park (IEEE Trans. Instrum. Meas., 2008)

Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults. - Jaehoon Song; Juhee Han; Hyunbean Yi; Taejin Jung; Sungju Park (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge. - Jaehoon Song; Hyunbean Yi; Juhee Han; Sungju Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Efficient Use of Unused Spare Columns to Improve Memory Error Correcting Rate. - Umair Ishaq; Jihun Jung; Jaehoon Song; Sungju Park (Asian Test Symposium, 2011)