Performance of an Operating High Energy Physics Data Grid: DØSAR-Grid - B. Abbott; P. Baringer; T. Bolton; Zeno Greenwood; E. Gregores; H. Kim; Chokchai Leangsuksun; D. Meyer; N. Mondal; S. Novaes; B. Quinn; Horst Severini; et al. (CoRR, 2005)

Implementation of AV Streaming System Using Peer-to-Peer Communication. - Norihiro Ishikawa; Hiroshi Tsutsui; Jaehoon Yu; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura; Takaaki Komura; Yoshitaka Uchida (CCNC, 2007)

A Speed-Up Scheme Based on Multiple-Instance Pruning for Pedestrian Detection Using a Support Vector Machine. - Jaehoon Yu; Ryusuke Miyamoto; Takao Onoye (IEEE Trans. Image Process., 2013)

An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology. - Tomoki Sugiura; Shoko Nakatsuka; Jaehoon Yu; Yoshinori Takeuchi; Masaharu Imai (BioCAS, 2014)

Normalized channel features for accurate pedestrian detection. - Ryusuke Miyamoto; Jaehoon Yu; Takao Onoye (ISCCSP, 2014)

Corrections to "A Speed-Up Scheme Based on Multiple-Instance Pruning for Pedestrian Detection Using a Support Vector Machine". - Jaehoon Yu; Ryusuke Miyamoto; Takao Onoye (IEEE Trans. Image Process., 2014)

A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems. - Tomoki Sugiura; Jaehoon Yu; Yoshinori Takeuchi; Masaharu Imai (BioCAS, 2015)

Design of generic hardware for soft cascade-based linear SVM classification. - Eric Aliwarga; Jaehoon Yu; Masahide Hatanaka; Takao Onoye (ISPACS, 2015)

A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis. - Tomoki Sugiura; Arif Ullah Khan; Jaehoon Yu; Yoshinori Takeuchi; Seiji Kameda; Takatsugu Kamata; Yuki Hayashida; Tetsuya Yagi; Masaharu Imai (BioCAS, 2016)

Hardware-oriented algorithm for phase synchronization analysis of biomedical signals. - Tomoki Sugiura; Jaehoon Yu; Yoshinori Takeuchi (BioCAS, 2017)

Deformable Part Model Based Arrhythmia Detection Using Time Domain Features. - Yuuka Hirao; Yoshinori Takeuchi; Masaharu Imai; Jaehoon Yu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems. - Tomoki Sugiura; Masaharu Imai; Jaehoon Yu; Yoshinori Takeuchi (J. Inf. Process., 2017)

Hardware Architecture for Fast General Object Detection using Aggregated Channel Features. - Koichi Mitsunari; Jaehoon Yu; Masanori Hashimoto (A-SSCC, 2018)

Sneak path free reconfiguration of via-switch crossbars based FPGA. - Ryutaro Doi; Jaehoon Yu; Masanori Hashimoto (ICCAD, 2018)

Interconnect Delay Analysis for RRAM Crossbar Based FPGA. - Masanori Hashimoto; Yuki Nakazawa; Ryutaro Doi; Jaehoon Yu (ISVLSI, 2018)

Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation. - Koichi Mitsunari; Yoshinori Takeuchi; Masaharu Imai; Jaehoon Yu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble. - Koichi Mitsunari; Jaehoon Yu; Takao Onoye; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Phase Locking Value Calculator Based on Hardware-Oriented Mathematical Expression. - Tomoki Sugiura; Jaehoon Yu; Yoshinori Takeuchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. - Hiroyuki Ochi; Kosei Yamaguchi; Tetsuaki Fujimoto; Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Takashi Imagawa; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Wataru Takahashi 002; Kazutoshi Wakabayashi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Distilling Knowledge for Non-Neural Networks. - Shota Fukui; Jaehoon Yu; Masanori Hashimoto (APSIPA, 2019)

Training Data Reduction using Support Vectors for Neural Networks. - Toranosuke Tanio; Kouya Takeda; Jaehoon Yu; Masanori Hashimoto (APSIPA, 2019)

Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier. - TaiYu Cheng; Jaehoon Yu; Masanori Hashimoto (PATMOS, 2019)

Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA. - Salita Sombatsiri; Seiya Shibata; Yuki Kobayashi; Hiroaki Inoue; Takashi Takenaka; Takeo Hosomi; Jaehoon Yu; Yoshinori Takeuchi (IPSJ Trans. Syst. LSI Des. Methodol., 2019)

Memory Efficient Training using Lookup-Table-based Quantization for Neural Network. - Kazuki Onishi; Jaehoon Yu; Masanori Hashimoto (AICAS, 2020)

ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training. - Shungo Kumazawa; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (CANDAR, 2020)

ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. - Junnosuke Suzuki; Kota Ando; Kazutoshi Hirose; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (CANDAR, 2020)

Low-Cost Reservoir Computing using Cellular Automata and Random Forests. - Ángel López García-Arias; Jaehoon Yu; Masanori Hashimoto (ISCAS, 2020)

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. - Masanori Hashimoto; Xu Bai; Naoki Banno; Munehiro Tada; Toshitsugu Sakamoto; Jaehoon Yu; Ryutaro Doi; Yusuke Araki; Hidetoshi Onodera; Takashi Imagawa; Hiroyuki Ochi; Kazutoshi Wakabayashi; et al. (ISSCC, 2020)

Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training. - TaiYu Cheng; Yukata Masuda; Jun Chen; Jaehoon Yu; Masanori Hashimoto (Integr., 2020)

Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA. - Ryutaro Doi; Jaehoon Yu; Masanori Hashimoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. - Ángel López García-Arias; Masanori Hashimoto; Masato Motomura; Jaehoon Yu (BMVC, 2021)

MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. - Takashi Imagawa; Jaehoon Yu; Masanori Hashimoto; Hiroyuki Ochi (DATE, 2021)

A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning. - Thiem Van Chu; Ryuichi Kitajima; Kazushi Kawamura; Jaehoon Yu; Masato Motomura (FPT, 2021)

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. - Kota Ando; Jaehoon Yu; Kazutoshi Hirose; Hiroki Nakahara; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (HCS, 2021)

Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture. - Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Jaehoon Yu; Masato Motomura (IEEE Access, 2021)

ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training. - Shungo Kumazawa; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (Int. J. Netw. Comput., 2021)

ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. - Junnosuke Suzuki; Tomohiro Kaneko; Kota Ando; Kazutoshi Hirose; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (Int. J. Netw. Comput., 2021)

Multicoated Supermasks Enhance Hidden Networks. - Yasuyuki Okoshi; Ángel López García-Arias; Kazutoshi Hirose; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (ICML, 2022)

APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control. - Daiki Okonogi; Satoru Jimbo; Kota Ando; Thiem Van Chu; Jaehoon Yu; Masato Motomura; Kazushi Kawamura (IPDPS Workshops, 2022)

Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. - Kazutoshi Hirose; Jaehoon Yu; Kota Ando; Yasuyuki Okoshi; Ángel López García-Arias; Junnosuke Suzuki; Thiem Van Chu; Kazushi Kawamura; Masato Motomura (ISSCC, 2022)

Investigating Small Device Implementation of FRET-based Optical Reservoir Computing. - Masafumi Tanakal; Jaehoon Yu; Masaki Nakagawa; Naoya Tate; Masanori Hashimoto (MWSCAS, 2022)

A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers. - Satoru Jimbo; Daiki Okonogi; Kota Ando; Thiem Van Chu; Jaehoon Yu; Masato Motomura; Kazushi Kawamura (IEICE Trans. Inf. Syst., 2022)

Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance. - Genta Inoue; Daiki Okonogi; Thiem Van Chu; Jaehoon Yu; Masato Motomura; Kazushi Kawamura (COOL CHIPS, 2023)

Decision Forest Training Accelerator Based on Binary Feature Decomposition. - Thiem Van Chu; Yu Mizutani; Yuta Nagahara; Shungo Kumazawa; Kazushi Kawamura; Jaehoon Yu; Masato Motomura (FCCM, 2023)

Samsung PIM/PNM for Transfmer Based AI : Energy Efficiency on PIM/PNM Cluster. - Jin Hyun Kim; Yuhwan Ro; Jinin So; Sukhan Lee 002; Shinhaeng Kang; YeonGon Cho; Hyeonsu Kim; Byeongho Kim; Kyungsoo Kim 003; Sangsoo Park; Jin-Seong Kim; Sanghoon Cha; et al. (HCS, 2023)

Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. - Kazushi Kawamura; Jaehoon Yu; Daiki Okonogi; Satoru Jimbo; Genta Inoue; Akira Hyodo; Ángel López García-Arias; Kota Ando; Bruno Hideki Fukushima-Kimura; Ryota Yasudo; Thiem Van Chu; Masato Motomura (ISSCC, 2023)

A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. - Mari Yasunaga; Junnosuke Suzuki; Masato Watanabe; Kazushi Kawamura; Thiem Van Chu; Jaehoon Yu; Masato Motomura (MCSoC, 2023)

Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (VLSI Technology and Circuits, 2023)

Recurrent Residual Networks Contain Stronger Lottery Tickets. - Ángel López García-Arias; Yasuyuki Okoshi; Masanori Hashimoto; Masato Motomura; Jaehoon Yu (IEEE Access, 2023)

TT-MLP: Tensor Train Decomposition on Deep MLPs. - Jiale Yan; Kota Ando; Jaehoon Yu; Masato Motomura (IEEE Access, 2023)

A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems. - Daiki Okonogi; Satoru Jimbo; Kota Ando; Thiem Van Chu; Jaehoon Yu; Masato Motomura; Kazushi Kawamura (IEICE Trans. Inf. Syst., 2023)

WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression. - Yasuyuki Okoshi; Ángel López García-Arias; Jaehoon Yu; Junnosuke Suzuki; Hikari Otsuka; Thiem Van Chu; Kazushi Kawamura; Daichi Fujiki; Masato Motomura (A-SSCC, 2024)

Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA. - Masato Watanabe; Shungo Kumazawa; Thiem Van Chu; Kazushi Kawamura; Jaehoon Yu; Masato Motomura (ICCE, 2024)

Toward Improving Ensemble-Based Collaborative Inference at the Edge. - Shungo Kumazawa; Jaehoon Yu; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (IEEE Access, 2024)

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (IEEE Access, 2024)

The Breakthrough Memory Solutions for Improved Performance on LLM Inference. - Byeongho Kim; Sanghoon Cha; Sangsoo Park; Jieun Lee; Sukhan Lee 002; Shinhaeng Kang; Jinin So; Kyungsoo Kim 003; Jin Jung; Jong-Geon Lee; Sunjung Lee; Yoonah Paik; et al. (IEEE Micro, 2024)

WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration. - Ángel López García-Arias; Yasuyuki Okoshi; Jaehoon Yu; Junnosuke Suzuki; Hikari Otsuka; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Masato Motomura (IEEE Access, 2025)