A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations. - Sangsu Lee; Jaehun Jun; Chulwoo Kim (ISOCC, 2017)

29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. - Yeonho Lee 002; Yoonjae Choi; Sang-Geun Bae; Jaehun Jun; Junyoung Song; Sewook Hwang; Chulwoo Kim (ISSCC, 2017)

A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System. - Jaehun Jun; Sang-Geun Bae; Yeonho Lee 002; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process. - Jaehun Jun; Jaegeun Song; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Hybrid Concurrent Driving Technique for Large Touch Screen Panels. - Malik Summair Asghar; Saad Arslan; HyungWon Kim 001; Jaehun Jun; Hyunkyu Park 005 (ISOCC, 2019)

12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. - Yeonho Lee 002; Yoonjae Choi; Junyoung Song; Sewook Hwang; Sang-Geun Bae; Jaehun Jun; Chulwoo Kim (IEEE J. Solid State Circuits, 2019)

Near threshold voltage digital PLL using low voltage optimised blocks for AR display system. - Jaehun Jun; Sangsu Lee; Chulwoo Kim (IET Circuits Devices Syst., 2020)

A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique. - Jaegeun Song; Jaehun Jun; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2020)