Technology Variability From a Design Perspective. - Borivoje Nikolic; Ji-Hoon Park; Jaehwa Kwak; Bastien Giraud; Zheng Guo; Liang-Teck Pang; Seng Oon Toh; Ruzica Jevtic; Kun Qian 014; Costas J. Spanos (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 550-2260MHz self-adjustable clock generator in 28nm FDSOI. - Jaehwa Kwak; Borivoje Nikolic (A-SSCC, 2015)

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. - Yunsup Lee; Brian Zimmer; Andrew Waterman; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Henry Cook; Rimas Avizienis; et al. (Hot Chips Symposium, 2015)

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (VLSIC, 2015)

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC. - Ben Keller; Martin Cochet; Brian Zimmer; Yunsup Lee; Milovan Blagojevic; Jaehwa Kwak; Alberto Puggelli; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (ESSCIRC, 2016)

A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI. - Jaehwa Kwak; Borivoje Nikolic (IEEE J. Solid State Circuits, 2016)

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Steven Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (IEEE J. Solid State Circuits, 2016)

An Agile Approach to Building RISC-V Microprocessors. - Yunsup Lee; Andrew Waterman; Henry Cook; Brian Zimmer; Ben Keller; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Rimas Avizienis; et al. (IEEE Micro, 2016)

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI. - Ben Keller; Martin Cochet; Brian Zimmer; Jaehwa Kwak; Alberto Puggelli; Yunsup Lee; Milovan Blagojevic; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (IEEE J. Solid State Circuits, 2017)

A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. - John Charles Wright; Colin Schmidt 001; Ben Keller; Daniel Palmer Dabbelt; Jaehwa Kwak; Vighnesh Iyer; Nandish Mehta; Pi-Feng Chiu; Stevo Bailey; Krste Asanovic; Borivoje Nikolic (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Efficient Tensor Slicing for Multicore NPUs using Memory Burst Modeling. - Rafael C. F. Sousa; Byungmin Jung; Jaehwa Kwak; Michael Frank 008; Guido Araujo (SBAC-PAD, 2021)