A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. - Daewoong Lee; Hye-Jung Kwon; Daehyun Kwon; Jaehyeok Baek; Chulhee Cho; Sanghoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (ISSCC, 2022)

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ. - Daewoong Lee; Jaehyeok Baek; Hye-Jung Kwon; Daehyun Kwon; Chulhee Cho; Sang-Hoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (IEEE J. Solid State Circuits, 2023)

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sanghoon Kim; Daewoong Lee; Seongyeal Yang; Gil-Young Kang; Juseop Park; Kyungho Lee; Hwan-Chul Jung; Gun-hee Cho; et al. (ISSCC, 2024)

30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction. - Sang-Hoon Kim; Jaehyeok Baek; Moon-Chul Choi; Daewoong Lee; Donggun An; Se-Mi Kim; Yeonggeun Song; Minkyo Shim; Sung-Yong Cho; Dongha Lee; Gun-hee Cho; Inwoo Jun; et al. (ISSCC, 2025)

A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sang-Hoon Kim; Daewoong Lee; Seongyeal Yang; Se-Mi Kim; Gil-Young Kang; Juseop Park; Kyung-Ho Lee; Hwan-Chul Jung; et al. (IEEE J. Solid State Circuits, 2025)