Subthreshold current mode matrix determinant computation for analog signal processing. - Stephen T. Kim; Jaehyouk Choi; Sungho Beck; Taejoong Song; Kyutae Lim; Joy Laskar (ISCAS, 2010)

A 122-mW Low-Power Multiresolution Spectrum-Sensing IC With Self-Deactivated Partial Swing Techniques. - Taejoong Song; Jongmin Park; Sang Min Lee; Jaehyouk Choi; Kihong Kim; Chang-Ho Lee; Kyutae Lim; Joy Laskar (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Fully-integrated DLL/PLL-based CMOS frequency synthesizers for wireless systems. - Jaehyouk Choi (2010)

A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor. - Jaehyouk Choi; Stephen T. Kim; Woonyun Kim; Kwan-Woo Kim; Kyutae Lim; Joy Laskar (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A 65nm CMOS current controlled oscillator with high tuning linearity for wideband polar modulation. - Yiwu Tang; Jianyun Hu; Jongmin Park; Jaehyouk Choi; Lincoln Leung; Chiewcharn Narathong; Kamal Sahota (CICC, 2012)

A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL. - Jaehyouk Choi; Woonyun Kim; Kyutae Lim (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A CMOS Highly Linear Hybrid Current/Voltage Controlled Oscillator for Wideband Polar Modulation. - Yiwu Tang; Jianyun Hu; Jongmin Park; Jaehyouk Choi; Lincoln Leung; Chiewcharn Narathong; Kamal Sahota (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration. - Taeho Seong; Yongsun Lee; Jaehyouk Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core. - Heein Yoon; Yongsun Lee; Jae Joon Kim; Jaehyouk Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells. - Mina Kim; Seojin Choi; Jaehyouk Choi (VLSIC, 2015)

Optimization of analog circuits via simulation and a lagrangian-type gradient-based method. - Eunji Lim; Youngmin Kim; Jaehyouk Choi (WSC, 2015)

A Wide-Range On-Chip Leakage Sensor Using a Current-Frequency Converting Technique in 65-nm Technology Node. - Yesung Kang; Jaehyouk Choi; Youngmin Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Reconfigurable Multiphase $LC$-Ring Structure for Programmable Frequency Multiplication. - Donguk Kim; Subin Choi; Jaehyouk Choi; Jae Joon Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs. - Yongsun Lee; Mina Kim; Taeho Seong; Jaehyouk Choi (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers. - Taeho Seong; Jae Joon Kim; Jaehyouk Choi (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

10.7 A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector. - Seojin Choi; Seyeon Yoo; Jaehyouk Choi (ISSCC, 2016)

A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop. - Yongsun Lee; Heein Yoon; Mina Kim; Jaehyouk Choi (VLSI Circuits, 2016)

A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector. - Seojin Choi; Seyeon Yoo; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2016)

A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells. - Mina Kim; Seojin Choi; Taeho Seong; Jaehyouk Choi (IEEE J. Solid State Circuits, 2016)

A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers. - Heein Yoon; Yongsun Lee; Younghyun Lim; Geum-Young Tak; Hong-Teuk Kim; Yo-Chuol Ho; Jaehyouk Choi (IEEE J. Solid State Circuits, 2016)

An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration. - Suneui Park; Heein Yoon; Jaehyouk Choi (A-SSCC, 2017)

An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate. - Younghyun Lim; Jeonghyun Lee; Suneui Park; Jaehyouk Choi (CICC, 2017)

19.2 A PVT-robust -39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers. - Seyeon Yoo; Seojin Choi; Juyeop Kim; Heein Yoon; Yongsun Lee; Jaehyouk Choi (ISSCC, 2017)

An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current. - Younghyun Lim; Jeonghyun Lee; Yongsun Lee; Seong-Sik Song; Hong-Teuk Kim; Ockgoo Lee; Jaehyouk Choi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A switched-loop-filter PLL with fast phase-error correction technique. - Yongsun Lee; Taeho Seong; Seyeon Yoo; Jaehyouk Choi (ASP-DAC, 2018)

An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate. - Younghyun Lim; Jeonghyun Lee; Suneui Park; Jaehyouk Choi (ASP-DAC, 2018)

Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers. - Seyeon Yoo; Seojin Choi; Juyeop Kim; Heein Yoon; Yongsun Lee; Jaehyouk Choi (ASP-DAC, 2018)

A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector. - Younghyun Lim; Jeonghyun Lee; Yongsun Lee; Seyeon Yoo; Jaehyouk Choi (ESSCIRC, 2018)

Session 15 overview: RF PLLs: RF subcommittee. - Jiayoon Ru; Jaehyouk Choi; Piet Wambacq (ISSCC, 2018)

A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC. - Taeho Seong; Yongsun Lee; Seyeon Yoo; Jaehyouk Choi (ISSCC, 2018)

A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers. - Heein Yoon; Juyeop Kim; Suneui Park; Younghyun Lim; Yongsun Lee; Jooeun Bang; Kyoohyun Lim; Jaehyouk Choi (ISSCC, 2018)

153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier. - Seojin Choi; Seyeon Yoo; Yongsun Lee; Yongwoo Jo; Jeonghyun Lee; Younghyun Lim; Jaehyouk Choi (VLSI Circuits, 2018)

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique. - Yongsun Lee; Taeho Seong; Seyeon Yoo; Jaehyouk Choi (IEEE J. Solid State Circuits, 2018)

A 65-nm CMOS 2×2 MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations. - Kyoohyun Lim; Sanghoon Lee; Yongha Lee; Byeongmoo Moon; Hwahyeong Shin; Kisub Kang; Seungbeom Kim; Jinhyeok Lee; Hyungsuk Lee; Hyunchul Shim; Chulhoon Sung; Kumyoung Park; et al. (IEEE J. Solid State Circuits, 2018)

An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique. - Younghyun Lim; Jeonghyun Lee; Suneui Park; Yongwoo Jo; Jaehyouk Choi (IEEE J. Solid State Circuits, 2018)

A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers. - Seyeon Yoo; Seojin Choi; Juyeop Kim; Heein Yoon; Yongsun Lee; Jaehyouk Choi (IEEE J. Solid State Circuits, 2018)

A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization. - Juyeop Kim; Heein Yoon; Younghyun Lim; Yongsun Lee; Yoonseo Cho; Taeho Seong; Jaehyouk Choi (ISSCC, 2019)

A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator. - Seyeon Yoo; Seojin Choi; Yongsun Lee; Taeho Seong; Younghyun Lim; Jaehyouk Choi (ISSCC, 2019)

A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer. - Jeonghyun Lee; Jooeun Bang; Younghyun Lim; Jaehyouk Choi (VLSI Circuits, 2019)

An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114. - Seojin Choi; Seyeon Yoo; Yongsun Lee; Yongwoo Jo; Jeonghyun Lee; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2019)

An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators. - Juyeop Kim; Younghyun Lim; Heein Yoon; Yongsun Lee; Hangi Park; Yoonseo Cho; Taeho Seong; Jaehyouk Choi (IEEE J. Solid State Circuits, 2019)

A 320-fs RMS Jitter and - 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC. - Taeho Seong; Yongsun Lee; Seyeon Yoo; Jaehyouk Choi (IEEE J. Solid State Circuits, 2019)

A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration. - Heein Yoon; Suneui Park; Jaehyouk Choi (IEEE J. Solid State Circuits, 2019)

17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction. - Yongsun Lee; Taeho Seong; Jeonghyun Lee; Chanwoong Hwang; Hangi Park; Jaehyouk Choi (ISSCC, 2020)

17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator. - Younghyun Lim; Juyeop Kim; Yongwoo Jo; Jooeun Bang; Seyeon Yoo; Hangi Park; Heein Yoon; Jaehyouk Choi (ISSCC, 2020)

17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word. - Taeho Seong; Yongsun Lee; Chanwoong Hwang; Jeonghyun Lee; Hangi Park; Kyuho Jason Lee; Jaehyouk Choi (ISSCC, 2020)

Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). - David T. Blaauw; Hoi Lee; John P. Keane; Jaehyouk Choi; Sudhakar Pamarti (IEEE J. Solid State Circuits, 2020)

A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency. - Jooeun Bang; Seojin Choi; Seyeon Yoo; Jeonghyun Lee; Juyeop Kim; Jaehyouk Choi (ESSCIRC, 2021)

Session 32 Overview: Frequency Synthesizers Rf Subcommittee. - Wei Deng; Jaehyouk Choi; Wanghua Wu (ISSCC, 2021)

32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique. - Juyeop Kim; Yongwoo Jo; Younghyun Lim; Taeho Seong; Hangi Park; Seyeon Yoo; Yongsun Lee; Seojin Choi; Jaehyouk Choi (ISSCC, 2021)

A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM. - Hangi Park; Chanwoong Hwang; Taeho Seong; Yongsun Lee; Jaehyouk Choi (ISSCC, 2021)

An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS. - Seyeon Yoo; Suneui Park; Seojin Choi; Yoonseo Cho; Heein Yoon; Chanwoong Hwang; Jaehyouk Choi (ISSCC, 2021)

A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator. - Seyeon Yoo; Seojin Choi; Yongsun Lee; Taeho Seong; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2021)

A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. - Chanwoong Hwang; Hangi Park; Taeho Seong; Jaehyouk Choi (ISSCC, 2022)

A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator. - Suneui Park; Seyeon Yoo; Yuhwan Shin; Jeonghyun Lee; Jaehyouk Choi (ISSCC, 2022)

A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. - Chanwoong Hwang; Hangi Park; Yongsun Lee; Taeho Seong; Jaehyouk Choi (IEEE J. Solid State Circuits, 2022)

A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop. - Younghyun Lim; Juyeop Kim; Yongwoo Jo; Jooeun Bang; Jaehyouk Choi (IEEE J. Solid State Circuits, 2022)

An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector. - Suneui Park; Seojin Choi; Seyeon Yoo; Yoonseo Cho; Jaehyouk Choi (IEEE J. Solid State Circuits, 2022)

A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. - Hangi Park; Chanwoong Hwang; Taeho Seong; Jaehyouk Choi (IEEE J. Solid State Circuits, 2022)

A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter. - Jeonghyun Lee; Yoonseo Cho; Jintae Kim; Jaehyouk Choi (CICC, 2023)

A $47 text{fs}_{ text{rms}}$-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth. - Jooeun Bang; Jaeho Kim; Seohee Jung; Suneui Park; Jaehyouk Choi (ISSCC, 2023)

A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier. - Yongwoo Jo; Juyeop Kim; Yuhwan Shin; Chanwoong Hwang; Hangi Park; Jaehyouk Choi (ISSCC, 2023)

A 264-to-287GHz, -2.5dBm Output Power, and -92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL. - Byeong-Taek Moon; Sang-Gug Lee 001; Jaehyouk Choi (ISSCC, 2023)

A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces. - Yuhwan Shin; Yongwoo Jo; Juyeop Kim; Junseok Lee; Jongwha Kim; Jaehyouk Choi (ISSCC, 2023)

A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique. - Yoonseo Cho; Jeonghyun Lee; Suneui Park; Seyeon Yoo; Jaehyouk Choi (VLSI Technology and Circuits, 2023)

A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68. - Suneui Park; Seyeon Yoo; Yuhwan Shin; Jeonghyun Lee; Jaehyouk Choi (IEEE J. Solid State Circuits, 2023)

A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier. - Yongwoo Jo; Juyeop Kim; Yuhwan Shin; Hangi Park; Chanwoong Hwang; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2023)

A -51dBc-Reference-Spur and 66fsrms-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector. - Jaeho Kim; Jooeun Bang; Seohee Jung; Myeongho Han; Jaehyouk Choi (A-SSCC, 2024)

10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm. - Seheon Jang; Munjae Chae; Hangi Park; Chanwoong Hwang; Jaehyouk Choi (ISSCC, 2024)

10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique. - Yuhwan Shin; Junseok Lee; Juyeop Kim; Yongwoo Jo; Jaehyouk Choi (ISSCC, 2024)

A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation. - Juyeop Kim; Yongwoo Jo; Hangi Park; Taeho Seong; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2024)

A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm. - Seheon Jang; Munjae Chae; Hangi Park; Chanwoong Hwang; Jaehyouk Choi (IEEE J. Solid State Circuits, 2024)

34.1 A 65fsrms-Jitter and -272dB-FoMjitter, N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration. - Munjae Chae; Seheon Jang; Chanwoong Hwang; Hangi Park; Jaehyouk Choi (ISSCC, 2025)

8.5 A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time. - Jaeho Kim; Myeongho Han; Jooeun Bang; Younghyun Lim; Jaehyouk Choi (ISSCC, 2025)

22.2: An 850µW 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Distribution in HBM Interfaces. - Jeongbeom Seo; Yoonseo Cho; Yuhwan Shin; Jaehyouk Choi (ISSCC, 2025)

A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator. - Yoonseo Cho; Jeonghyun Lee; Suneui Park; Seyeon Yoo; Jaehyouk Choi (IEEE J. Solid State Circuits, 2025)

A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces. - Yuhwan Shin; Yongwoo Jo; Juyeop Kim; Junseok Lee; Jongwha Kim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2025)

A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer With a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier. - Seohee Jung; Jaeho Kim; Jooeun Bang; Sarang Lee; Heein Yoon; Jaehyouk Choi (IEEE J. Solid State Circuits, 2025)