Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations. - Hyejeong Hong; Jaeil Lim; Hyunyul Lim; Sungho Kang 001 (IEICE Electron. Express, 2013)

Dynamic thermal management for 3D multicore processors under process variations. - Hyejeong Hong; Jaeil Lim; Hyunyul Lim; Sungho Kang 001 (IEICE Electron. Express, 2013)

Recovery-enhancing task scheduling for multicore processors under NBTI impact. - Hyejeong Hong; Jaeil Lim; Sungho Kang 001 (IEICE Electron. Express, 2014)

Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability. - Hyejeong Hong; Jaeil Lim; Hyunyul Lim; Sungho Kang 001 (ACM Comput. Surv., 2015)

3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability. - Jaeil Lim; Hyunyul Lim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Process variation-aware bridge fault analysis. - Heetae Kim; Inhyuk Choi; Jaeil Lim; Hyunggoy Oh; Sungho Kang 001 (ISOCC, 2016)

A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. - Hyunggoy Oh; Heetae Kim; Jaeil Lim; Sungho Kang 001 (ISOCC, 2017)

A novel X-filling method for capture power reduction. - Heetae Kim; Hyunggoy Oh; Jaeil Lim; Sungho Kang 001 (IEICE Electron. Express, 2017)

Reconfigurable scan architecture for test power and data volume reduction. - Hyunggoy Oh; Heetae Kim; Jaeil Lim; Sungho Kang 001 (IEICE Electron. Express, 2017)

Thermal Aware Test Scheduling for NTV Circuit. - Jaeil Lim; Hyunggoy Oh; Heetae Kim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A New ECC Configuration Method for DRAM System Considering Metadata. - Jaeil Lim; Jaewon Chung; Donghun Jeong; Daegeun Jee; Euicheol Lim (IEEE Trans. Computers, 2025)