A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter. - Daejong Kim; Jaejin Park; Sungjoon Kim; Deog-Kyoon Jeong; Wonchan Kim (ISCAS, 1994)

A single chip iΔ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem. - Daejeong Kim; Jaejin Park; Sungjoon Kim; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 1995)

A 5-MHz IF digital FM demodulator. - Jaejin Park; Eurho Joe; Myung-Jun Choe; Bang-Sup Song (IEEE J. Solid State Circuits, 1999)

A 1 mW 10-bit 500KSPS SAR A/D converter. - Jaejin Park; Ho-Jin Park; Jae-Whui Kim; Sangnam Seo; Philip Chung 003 (ISCAS, 2000)

A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs. - Jaejin Park; Ruifeng Sun; L. Rick Carley; C. Patrick Yue (ISCAS (2), 2005)

A low-power, 20-Gb/s continuous-time adaptive passive equalizer. - Ruifeng Sun; Jaejin Park; Frank O'Mahony; C. Patrick Yue (ISCAS (2), 2005)

A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR. - Jaejin Park; J. F. Liu; L. Richard Carley; C. Patrick Yue (CICC, 2007)

FTFD: an informatics pipeline supporting phylogenomic analysis of fungal transcription factors. - Jongsun Park 002; Jaejin Park; Suwang Jang; Seryun Kim; Sunghyung Kong; Jaeyoung Choi; Kyohun Ahn; Juhyeon Kim; Seungmin Lee; Sunggon Kim; Bongsoo Park; Kyongyong Jung; et al. (Bioinform., 2008)

CFGP: a web-based, comparative fungal genomics platform. - Jongsun Park 002; Bongsoo Park; Kyongyong Jung; Suwang Jang; Kwangyul Yu; Jaeyoung Choi; Sunghyung Kong; Jaejin Park; Seryun Kim; Hyojeong Kim; Soonok Kim; Jihyun F. Kim; et al. (Nucleic Acids Res., 2008)

A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS. - Jenlung Liu; Sehyung Jeon; Tae-Kwang Jang; Dohyung Kim; Jihyun F. Kim; Jaejin Park; Hojin Park (A-SSCC, 2011)

A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications. - Jong-Phil Hong; Sung-Jin Kim; Jenlung Liu; Nan Xing; Tae-Kwang Jang; Jaejin Park; Jihyun F. Kim; Taeik Kim; Hojin Park (ISSCC, 2012)

An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS. - Pyoungwon Park; Jaejin Park; Hojin Park; SeongHwan Cho (ISSCC, 2012)

Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization. - Taehwan Kim 007; Do-Gyoon Song; Sangho Youn; Jaejin Park; Hojin Park; Jaeha Kim (ICCAD, 2013)

A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter. - Tae-Kwang Jang; Nan Xing; Frank Liu 003; Jungeun Shin; Hyungreal Ryu; Jihyun F. Kim; Taeik Kim; Jaejin Park; Hojin Park (ISSCC, 2013)

A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. - Wooseok Kim; Jaejin Park; Jihyun F. Kim; Taeik Kim; Hojin Park; Deog-Kyoon Jeong (ISSCC, 2013)

15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider. - Jenlung Liu; Tae-Kwang Jang; Yonghee Lee; Jungeun Shin; Seunghoon Lee; Taeik Kim; Jaejin Park; Hojin Park (ISSCC, 2014)

Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. - Wooseok Kim; Jaejin Park; Hojin Park; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2014)

Session 12 overview: Efficient Power Conversion. - Vadim Ivanov; Jaejin Park (ISSCC, 2016)

A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. - Gyu-Seob Jeong; Wooseok Kim; Jaejin Park; Taeik Kim; Hojin Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)