A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. - Joseph T. Kennedy; Randy Mooney; Robert Ellis; James E. Jaussi; Shekhar Borkar; Jung-Hwan Choi; Jae-Kwan Kim 003; Chan-Kyong Kim; Woo-Seop Kim; Chang-Hyun Kim; Soo-In Cho; Steffen Loeffler; et al. (IEEE J. Solid State Circuits, 2005)

An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. - Kyu-Hyoun Kim; Uksong Kang; Hoeju Chung; Dukha Park; Woo-Seop Kim; Young-Chan Jang; Moon-Sook Park; Hoon Lee; Jinyoung Kim; Jung Sunwoo; Hwan-Wook Park; Hyun-Kyung Kim; et al. (ISSCC, 2006)

A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. - Churoo Park; Hoeju Chung; Yun-Sang Lee; Jaekwan Kim 003; JaeJun Lee; Moo Sung Chae; Dae-Hee Jung; Sung-Ho Choi; Seung-young Seo; Taek-Seon Park; Jun-Ho Shin; Jin-Hyung Cho; et al. (IEEE J. Solid State Circuits, 2006)

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel. - Young-Chan Jang; Hoeju Chung; Youngdon Choi; Hwan-Wook Park; Jaekwan Kim 003; Soouk Lim; Jung Sunwoo; Moon-Sook Park; Hyung-Seuk Kim; Sang-Yun Kim; Yun-Sang Lee; Woo-Seop Kim; et al. (IEEE J. Solid State Circuits, 2009)