Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces. - Jae-Whan Lee; Joo-Hyung Chae; Jihwan Park; Hyunkyu Park 002; Jaekwang Yun; Suhwan Kim 001 (ISLPED, 2018)

A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS. - Yong-Un Jeong; Joo-Hyung Chae; Sungphil Choi; Jaekwang Yun; Shin-Hyun Jeong; Suhwan Kim 001 (ISLPED, 2019)

A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. - Han-Gon Ko; Soyeong Shin; Chan-Ho Kye; Sang-Yoon Lee 006; Jaekwang Yun; Hae-Kang Jung; Doobock Lee; Suhwan Kim 001; Deog-Kyoon Jeong (VLSI Circuits, 2019)

A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction. - Jaekwang Yun; Sangyoon Lee 006; Yong-Un Jeong; Shin-Hyun Jeong; Suhwan Kim 001 (A-SSCC, 2020)

A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces. - Yong-Un Jeong; Jihwan Park; Mino Kim; Joo-Hyung Chae; Jaekwang Yun; Hyunjoong Lee; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. - Sangyoon Lee 006; Han-Gon Ko; Joo-Hyung Chae; Soyeong Shin; Jaekwang Yun; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. - Soyeong Shin; Han-Gon Ko; Chan-Ho Kye; Sang-Yoon Lee 006; Jaekwang Yun; Doobock Lee; Hae-Kang Jung; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS. - Sangyoon Lee 006; Jaekwang Yun; Suhwan Kim 001 (ISSCC, 2022)

A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces. - Yong-Un Jeong; Sungphil Choi; Joo-Hyung Chae; Jaekwang Yun; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching. - Sangyoon Lee 006; Yong-Un Jeong; Jaekwang Yun; Joo-Hyung Chae; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 50-1600 MHz Wide-Range Digital Duty-Cycle Corrector With Counter-Based Half-Cycle Delay Line. - Jaewook Kim; Jaekwang Yun; Joo-Hyung Chae; Suhwan Kim 001 (IEEE Access, 2023)

A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces. - Sanghyuk Seo; Yong-Un Jeong; Jaekwang Yun; Jaewook Kim; Suhwan Kim 001 (ISCAS, 2024)

A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces. - Jaekwang Yun; Sangyoon Lee 006; Jaewook Kim; Joo-Hyung Chae; Suhwan Kim 001; Yong-Un Jeong (IEEE J. Solid State Circuits, 2024)

An Energy and Area-Efficient PAM-4 Data Coding Scheme with Embedded Supply Noise Stabilization for Single-Ended Memory Interface. - Giyeong Heo; Younghwan Chang; Yong-Un Jeong; Jaekwang Yun; Jusung Lee; Shin-Hyun Jeong; Sanghyuk Seo; Suhwan Kim 001 (CICC, 2025)