Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification. - Jaekyung Im; Seokhyeong Kang (ISOCC, 2021)

Graph Partitioning Approach for Fast Quantum Circuit Simulation. - Jaekyung Im; Seokhyeong Kang (ASP-DAC, 2023)

Placement Initialization via Community Detection. - Junseok Hur; Jaekyung Im; Seokhyeong Kang (ISOCC, 2023)

SkyPlace: A New Mixed-size Placement Framework using Modularity-based Clustering and SDP Relaxation. - Jaekyung Im; Seokhyeong Kang (DAC, 2024)

Leveraging Machine Learning Techniques for Traditional EDA Workflow Enhancement. - Jinoh Cho; Jaekyung Im; Jaeseung Lee; Kyungjun Min; Seonghyeon Park; Jaemin Seo; Jongho Yoon 001; Seokhyeong Kang (ASP-DAC, 2025)