A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. - Kibong Koo; Sunghwa Ok; Yonggu Kang; Seungbong Kim; Choungki Song; Hyeyoung Lee; Hyungsoo Kim; Yongmi Kim; Jeonghun Lee; Seunghan Oak; Yosep Lee; Jungyu Lee 002; et al. (ISSCC, 2012)

Multiple clone row DRAM: a low latency and area optimized DRAM. - Jungwhan Choi; Wongyu Shin; Jaemin Jang; Jinwoong Suh; Yongkee Kwon; Youngsuk Moon; Lee-Sup Kim (ISCA, 2015)

Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity. - Hoseok Seol; Wongyu Shin; Jaemin Jang; Jungwhan Choi; Jinwoong Suh; Lee-Sup Kim (ISCA, 2016)

Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation. - Wongyu Shin; Jungwhan Choi; Jaemin Jang; Jinwoong Suh; Yongkee Kwon; Youngsuk Moon; Hongsik Kim; Lee-Sup Kim (IEEE Trans. Computers, 2016)

DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing. - Wongyu Shin; Jungwhan Choi; Jaemin Jang; Jinwoong Suh; Youngsuk Moon; Yongkee Kwon; Lee-Sup Kim (IEEE Trans. Computers, 2016)

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs. - Ji-Hoon Lim; Jun-Hyun Bae; Jaemin Jang; Hae-Kang Jung; Hyunbae Lee; Yongju Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A new application-layer overlay platform for better connected vehicles. - Jaemin Jang; Taemin Ahn; Junghee Han (Int. J. Distributed Sens. Networks, 2017)

Refresh-Aware Write Recovery Memory Controller. - Jaemin Jang; Wongyu Shin; Jungwhan Choi; Jinwoong Suh; Yongkee Kwon; Yongju Kim; Lee-Sup Kim (IEEE Trans. Computers, 2017)

Bank-Group Level Parallelism. - Wongyu Shin; Jaemin Jang; Jungwhan Choi; Jinwoong Suh; Lee-Sup Kim (IEEE Trans. Computers, 2017)

Rank-Level Parallelism in DRAM. - Wongyu Shin; Jaemin Jang; Jungwhan Choi; Jinwoong Suh; Yongkee Kwon; Youngsuk Moon; Lee-Sup Kim (IEEE Trans. Computers, 2017)

In-DRAM Data Initialization. - Hoseok Seol; Wongyu Shin; Jaemin Jang; Jungwhan Choi; Jinwoong Suh; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs. - Hoseok Seol; Wongyu Shin; Jaemin Jang; Jungwhan Choi; Hakseung Lee; Lee-Sup Kim (IEEE Trans. Computers, 2018)

DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells. - Jungwhan Choi; Jaemin Jang; Lee-Sup Kim (IEEE Trans. Computers, 2019)

Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory. - Jaemin Jang; Wongyu Shin; Jungwhan Choi; Yongju Kim; Lee-Sup Kim (IEEE Trans. Computers, 2019)

13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization. - Jinhyung Lee; Kyungjun Cho; Chang Kwon Lee; Yeonho Lee 002; Jae-Hyung Park; Su-Hyun Oh; Yucheon Ju; Chunseok Jeong; Ho Sung Cho; Jaeseung Lee; Tae-Sik Yun; Jin Hee Cho; et al. (ISSCC, 2024)