17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization. - Taejoong Song; Woojin Rim; Sunghyun Park 003; Yongho Kim; Jonghoon Jung; Giyong Yang; Sanghoon Baek; Jaeseung Choi 001; Bongjae Kwon; Yunwoo Lee; Sungbong Kim; Gyu-Hong Kim; et al. (ISSCC, 2016)

12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. - Taejoong Song; Hoonki Kim; Woojin Rim; Yongho Kim; Sunghyun Park 003; Changnam Park; Minsun Hong; Giyong Yang; Jeongho Do; Jinyoung Lim; Seungyoung Lee; Ingyum Kim; et al. (ISSCC, 2017)

A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization. - Taejoong Song; Woojin Rim; Sunghyun Park 003; Yongho Kim; Giyong Yang; Hoonki Kim; Sanghoon Baek; Jonghoon Jung; Bongjae Kwon; Sungwee Cho; Hyuntaek Jung; Yongjae Choo; et al. (IEEE J. Solid State Circuits, 2017)

A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications. - Taejoong Song; Jonghoon Jung; Woojin Rim; Hoonki Kim; Yongho Kim; Changnam Park; Jeongho Do; Sunghyun Park 003; Sungwee Cho; Hyuntaek Jung; Bongjae Kwon; Hyun-Su Choi; et al. (ISSCC, 2018)

A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology. - Inhak Lee; Hanwool Jeong; Sangyeop Baeck; Siddharth Gupta 008; Changnam Park; Dongwook Seo; Jaeseung Choi 001; Jaeyoung Kim; Hoon Kim; Jungmyung Kang; Sunyung Jang; Daeyoung Moon; et al. (ISSCC, 2019)

5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application. - Sangyeop Baeck; Inhak Lee; Hoyoung Tang; Dongwook Seo; Jaeseung Choi 001; Taejoong Song; Jongwook Kye (VLSI Circuits, 2021)

A 28nm Embedded Flash Memory with 100MHz Read Operation and 7.42Mb/mm2 at 0.85V featuring for Automotive Application. - Hyunjin Shin; Myeonghee Oh; Jaeseung Choi 001; Taejoong Song; Jongwook Kye (VLSI Circuits, 2021)

A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm2 at 0.85V. - Hyunjin Shin; Sangkyung Won; Dohui Kim; Byunghun Choi; Gyusung Kim; Myeonghee Oh; Jaeseung Choi 001; Jongwook Kye (VLSI Technology and Circuits, 2022)

A 14nm 128Mb Embedded MRAM Macro achieved the Best Figure-Of-Merit with 80MHz Read operation and 18.1Mb/mm² implementation at 0.64V. - Gyuseong Kang; Hyunjin Shin; Hyuntaek Jung; Sunkyu Lee; Jaeseung Choi 001; Sangyeop Baeck; Hyunsung Jung; Daeshik Kim; Sohee Hwang; Shinhee Han; Yongsung Ji; Sei Seung Yoon (VLSI Technology and Circuits, 2023)