FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion. - Jaewoong Sim; Jaekyu Lee; Moinuddin K. Qureshi; Hyesoon Kim (ISCA, 2012)

A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. - Jaewoong Sim; Gabriel H. Loh; Hyesoon Kim; Mike O'Connor; Mithuna Thottethodi (MICRO, 2012)

A performance analysis framework for identifying potential benefits in GPGPU applications. - Jaewoong Sim; Aniruddha Dasgupta; Hyesoon Kim; Richard W. Vuduc (PPoPP, 2012)

Resilient die-stacked DRAM caches. - Jaewoong Sim; Gabriel H. Loh; Vilas Sridharan; Mike O'Connor (ISCA, 2013)

Transparent Hardware Management of Stacked DRAM as Part of Memory. - Jaewoong Sim; Alaa R. Alameldeen; Zeshan Chishti; Chris Wilkerson; Hyesoon Kim (MICRO, 2014)

A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches. - Jaewoong Sim; Gabriel H. Loh; Vilas Sridharan; Mike O'Connor (IEEE Micro, 2014)

BSSync: Processing Near Memory for Machine Learning Workloads with Bounded Staleness Consistency Models. - Joo Hwan Lee; Jaewoong Sim; Hyesoon Kim (PACT, 2015)

Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. - Eriko Nurvitadhi; Jaewoong Sim; David Sheffield; Asit K. Mishra; Krishnan Srivatsan; Debbie Marr (FPL, 2016)

Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC. - Eriko Nurvitadhi; David Sheffield; Jaewoong Sim; Asit K. Mishra; Ganesh Venkatesh; Debbie Marr (FPT, 2016)

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? - Eriko Nurvitadhi; Ganesh Venkatesh; Jaewoong Sim; Debbie Marr; Randy Huang; Jason Ong Gee Hock; Yeong Tat Liew; Krishnan Srivatsan; Duncan J. M. Moss; Suchit Subhaschandra; Guy Boudoukh (FPGA, 2017)

High performance binary neural networks on the Xeon+FPGA™ platform. - Duncan J. M. Moss; Eriko Nurvitadhi; Jaewoong Sim; Asit K. Mishra; Debbie Marr; Suchit Subhaschandra; Philip Heng Wai Leong (FPL, 2017)

GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks. - Lifeng Nai; Ramyad Hadidi; Jaewoong Sim; Hyojong Kim; Pranith Kumar; Hyesoon Kim (HPCA, 2017)

A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study. - Duncan J. M. Moss; Krishnan Srivatsan; Eriko Nurvitadhi; Piotr Ratuszniak; Chris Johnson; Jaewoong Sim; Asit K. Mishra; Debbie Marr; Suchit Subhaschandra; Philip Heng Wai Leong (FPGA, 2018)

CoolPIM: Thermal-Aware Source Throttling for Efficient PIM Instruction Offloading. - Lifeng Nai; Ramyad Hadidi; He Xiao; Hyojong Kim; Jaewoong Sim; Hyesoon Kim (IPDPS, 2018)

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. - Eriko Nurvitadhi; Dongup Kwon; Ali Jafari; Andrew Boutros; Jaewoong Sim; Phillip Tomson; Huseyin Sumbul; Gregory K. Chen; Phil C. Knag; Raghavan Kumar; Ram Krishnamurthy 001; Sergey Gribok; et al. (FCCM, 2019)

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. - Eriko Nurvitadhi; Dongup Kwon; Ali Jafari; Andrew Boutros; Jaewoong Sim; Phillip Tomson; Huseyin Sumbul; Gregory K. Chen; Phil C. Knag; Raghavan Kumar; Ram Krishnamurthy 001; Debbie Marr; et al. (FPGA, 2019)

Thermal-aware processing-in-memory instruction offloading. - Lifeng Nai; Ramyad Hadidi; He Xiao; Hyojong Kim; Jaewoong Sim; Hyesoon Kim (J. Parallel Distributed Comput., 2019)

Batch-Aware Unified Memory Management in GPUs for Irregular Workloads. - Hyojong Kim; Jaewoong Sim; Prasun Gera; Ramyad Hadidi; Hyesoon Kim (ASPLOS, 2020)

Supporting CUDA for an extended RISC-V GPU architecture. - Ruobing Han; Blaise Tine; Jaewon Lee; Jaewoong Sim; Hyesoon Kim (CoRR, 2021)

COX: CUDA on X86 by Exposing Warp-Level Functions to CPUs. - Ruobing Han; Jaewon Lee; Jaewoong Sim; Hyesoon Kim (CoRR, 2021)

Specializing FGPU for Persistent Deep Learning. - Rui Ma; Jia-Ching Hsu; Tian Tan 007; Eriko Nurvitadhi; David Sheffield; Rob Pelt; Martin Langhammer; Jaewoong Sim; Aravind Dasu; Derek Chiou (ACM Trans. Reconfigurable Technol. Syst., 2021)

CuPBoP: CUDA for Parallelized and Broad-range Processors. - Ruobing Han; Jun Chen; Bhanu Garg; Jeffrey Young 001; Jaewoong Sim; Hyesoon Kim (CoRR, 2022)

COX : Exposing CUDA Warp-level Functions to CPUs. - Ruobing Han; Jaewon Lee; Jaewoong Sim; Hyesoon Kim (ACM Trans. Archit. Code Optim., 2022)

SDM: Sharing-Enabled Disaggregated Memory System with Cache Coherent Compute Express Link. - Hyokeun Lee; Kwanseok Choi; Hyuk-Jae Lee; Jaewoong Sim (PACT, 2023)

NeuRex: A Case for Neural Rendering Acceleration. - Junseo Lee; Kwanseok Choi; Jungi Lee; Seokwon Lee; Joonho Whangbo; Jaewoong Sim (ISCA, 2023)

CuPBoP: A Framework to Make CUDA Portable. - Ruobing Han; Jun Chen; Bhanu Garg; Jeffrey Young 001; Jaewoong Sim; Hyesoon Kim (PPoPP, 2023)

GSCore: Efficient Radiance Field Rendering via Architectural Support for 3D Gaussian Splatting. - Junseo Lee; Seokwon Lee; Jungi Lee; Junyong Park 005; Jaewoong Sim (ASPLOS (3), 2024)

MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models. - Taehyun Kim; Kwanseok Choi; Youngmock Cho; Jaehoon Cho; Hyuk-Jae Lee; Jaewoong Sim (DAC, 2024)

Tender: Accelerating Large Language Models via Tensor Decomposition and Runtime Requantization. - Jungi Lee; Wonbeom Lee; Jaewoong Sim (ISCA, 2024)

InfiniGen: Efficient Generative Inference of Large Language Models with Dynamic KV Cache Management. - Wonbeom Lee; Jungi Lee; Junghwan Seo; Jaewoong Sim (OSDI, 2024)

CuPBoP: Making CUDA a Portable Language. - Ruobing Han; Jun Chen; Bhanu Garg; Xule Zhou; John Lu; Jeffrey Young 001; Jaewoong Sim; Hyesoon Kim (ACM Trans. Design Autom. Electr. Syst., 2024)

VR-Pipe: Streamlining Hardware Graphics Pipeline for Volume Rendering. - Junseo Lee; Jaisung Kim; Junyong Park 005; Jaewoong Sim (HPCA, 2025)