Driving Virtual Human using the Hybrid of Position-based and Angle-based Control Mode. - Jaeyong Chung; Gwanghyun Shim; Byungtae Choi (Modelling, Simulation, and Optimization, 2003)

VENUS: The Online Game Simulator Using Massively Virtual Clients. - YungWoo Jung; Bum-Hyun Lim; Kwanghyun Sim; Hunjoo Lee; Ilkyu Park; Jaeyong Chung; Jihong Lee (AsiaSim, 2004)

Color Object Tracking System for Interactive Entertainment Applications. - Jaeyong Chung; Kwanghyun Shim (ICASSP (5), 2006)

A Dynamic Load Balancing for Massive Multiplayer Online Game Server. - Jungyoul Lim; Jaeyong Chung; Jin Ryong Kim; Kwanghyun Shim (ICEC, 2006)

LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits. - Joonsung Park; Jaeyong Chung; Jacob A. Abraham (Asian Test Symposium, 2009)

A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA. - Jaeyong Chung; Jacob A. Abraham (ICCAD, 2009)

Measuring temporal variation in presence during game playing. - Jaeyong Chung; Henry J. Gardner (VRCAI, 2009)

Recursive Path Selection for Delay Fault Testing. - Jaeyong Chung; Jacob A. Abraham (VTS, 2009)

At-speed Test of High-Speed DUT Using Built-Off Test Interface. - Joonsung Park; Jae Wook Lee; Jaeyong Chung; Kihyuk Han; Jacob A. Abraham; Eonjo Byun; Cheol-Jong Woo; Sejang Oh (Asian Test Symposium, 2010)

A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control. - Hyunjin Kim; Jaeyong Chung; Jacob A. Abraham; Eonjo Byun; Cheol-Jong Woo (ETS, 2010)

Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate. - Jaeyong Chung; Joonsung Park; Jacob A. Abraham; Eonjo Byun; Cheol-Jong Woo (VTS, 2010)

Path criticality computation in parameterized statistical timing analysis. - Jaeyong Chung; Jinjun Xiong; Vladimir Zolotov; Jacob A. Abraham (ASP-DAC, 2011)

Post-Silicon Timing Validation Method Using Path Delay Measurements. - Eun Jung Jang; Jaeyong Chung; Anne E. Gattiker; Sani R. Nassif; Jacob A. Abraham (Asian Test Symposium, 2011)

Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. - Kihyuk Han; Joonsung Park; Jae Wook Lee; Jaeyong Chung; Eonjo Byun; Cheol-Jong Woo; Sejang Oh; Jacob A. Abraham (J. Electron. Test., 2011)

Temporal Presence Variation in Immersive Computer Games. - Jaeyong Chung; Henry J. Gardner (Int. J. Hum. Comput. Interact., 2012)

Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA. - Jaeyong Chung; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

On Computing Criticality in Refactored Timing Graphs. - Jaeyong Chung; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator. - Jaeyong Chung; Jinjun Xiong; Vladimir Zolotov; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Testability-Driven Statistical Path Selection. - Jaeyong Chung; Jinjun Xiong; Vladimir Zolotov; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Concurrent Path Selection Algorithm in Statistical Timing Analysis. - Jaeyong Chung; Jacob A. Abraham (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories. - Jaeyong Chung; Joonsung Park; Jacob A. Abraham (IEEE Trans. Very Large Scale Integr. Syst., 2013)

3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations. - Jaeyong Chung; Yonghyun Kim; Joon-Sung Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

INsight: A Neuromorphic Computing System for Evaluation of Large Neural Networks. - Jaeyong Chung; Taehwan Shin; Yongshin Kang (CoRR, 2015)

Untangling polygonal and polyhedral meshes via mesh optimization. - Jibum Kim; Jaeyong Chung (Eng. Comput., 2015)

Delay Defect Diagnosis Methodology Using Path Delay Measurements. - Eun Jung Jang; Jaeyong Chung; Jacob A. Abraham (IEICE Trans. Electron., 2015)

QoS Management for Embedded Databases in Multicore-Based Embedded Systems. - Woochul Kang; Jaeyong Chung (Mob. Inf. Syst., 2015)

Bit-Width Optimization by Divide-and-Conquer for Fixed-Point Digital Signal Processing Systems. - Jaeyong Chung; Lok-Won Kim (IEEE Trans. Computers, 2015)

Segment Delay Learning From Quantized Path Delay Measurements. - Jaeyong Chung; Jibum Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Simplifying deep neural networks for neuromorphic architectures. - Jaeyong Chung; Taehwan Shin (DAC, 2016)

Live demonstration: Real-time image classification on a neuromorphic computing system with zero off-chip memory access. - Taehwan Shin; Yongshin Kang; Seungho Yang; Seban Kim; Jaeyong Chung (ISCAS, 2016)

Defect Diagnosis via Segment Delay Learning. - Jaeyong Chung; Woochul Kang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Synthesis of activation-parallel convolution structures for neuromorphic architectures. - Seban Kim; Jaeyong Chung (DATE, 2017)

A dynamic fixed-point representation for neuromorphic computing systems. - Yongshin Kang; Jaeyong Chung (ISOCC, 2017)

Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems. - Jaeyong Chung; Woochul Kang (IEICE Trans. Electron., 2017)

Energy-efficient response time management for embedded databases. - Woochul Kang; Jaeyong Chung (Real Time Syst., 2017)

New library development method by FSM based cell pattern extraction. - Byung-Su Kim; Tae Hee Han; Joon-Sung Yang; Jaeyong Chung (IEICE Electron. Express, 2018)

Dynamic Fixed-Point Design of Neuromorphic Computing Systems. - Yongshin Kang; Jaeyong Chung (IEICE Trans. Electron., 2018)

READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution. - Hyunseung Han; Jaeyong Chung; Joon-Sung Yang (IEEE Trans. Computers, 2018)

Mitigating Observability Loss of Toggle-Based X-Masking via Scan Chain Partitioning. - Sae-Eun Kim; Jaeyong Chung; Joon-Sung Yang (IEEE Trans. Computers, 2018)

Physical Workout Classification Using Wrist Accelerometer Data by Deep Convolutional Neural Networks. - Pilyeong Jeong; Mungyeong Choe; Nahyeong Kim; Jaehyun Park 004; Jaeyong Chung (IEEE Access, 2019)

Power- and Time-Aware Deep Learning Inference for Mobile Embedded Devices. - Woochul Kang; Jaeyong Chung (IEEE Access, 2019)

DeepRT: predictable deep learning inference for cyber-physical systems. - Woochul Kang; Jaeyong Chung (Real Time Syst., 2019)

Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems. - Jaeyong Chung; Taehwan Shin; Joon-Sung Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems. - Yongshin Kang; Joon-Sung Yang; Jaeyong Chung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Factored Radix-8 Systolic Array for Tensor Processing. - Inayat Ullah; Kashif Inayat; Joon-Sung Yang; Jaeyong Chung (DAC, 2020)

Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture. - Jeong-Hyeon Kim; Ho-Jun Jo; Kyung-Kuk Jo; Sung-Hee Cho; Jaeyong Chung; Joon-Sung Yang (DATE, 2020)

Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits. - Muhammad Imran 010; Hyunseung Han; Jooho Kim; Taehyun Kwon; Jaeyong Chung; Joon-Sung Yang (IEEE Access, 2020)

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs. - Inayat Ullah; Joon-Sung Yang; Jaeyong Chung (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Training Multi-Bit Quantized and Binarized Networks with a Learnable Symmetric Quantizer. - Phuoc Pham; Jacob A. Abraham; Jaeyong Chung (IEEE Access, 2021)

Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration. - Kashif Inayat; Jaeyong Chung (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Quickloop: An Efficient, FPGA-Accelerated Exploration of Parameterized DNN Accelerators. - Tayyeb Mahmood; Kashif Inayat; Jaeyong Chung (PACT, 2023)

AGD: A Learning-based Optimization Framework for EDA and its Application to Gate Sizing. - Phuoc Pham; Jaeyong Chung (DAC, 2023)

FPGA-assisted Design Space Exploration of Parameterized AI Accelerators: A Quickloop Approach. - Kashif Inayat; Fahad Bin Muslim; Tayyeb Mahmood; Jaeyong Chung (J. Syst. Archit., 2024)

Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration. - Kashif Inayat; Inayat Ullah; Jaeyong Chung (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Reducing Errors and Powers in LPDDR for DNN Inference: A Compression and IECC-Based Approach. - Jae-Youn Hong; Je-Woo Jang; Sung-Hyuk Cho; Youngbae Kong; Sungkyu Kim; Youngjung Kang; Jaehyung Ko; Jaeyong Chung; Joon-Sung Yang (J. Syst. Archit., 2025)