The chalcogenide-based memory technology continues: beyond 20nm 4-deck 256Gb cross-point memory. - Jaeyun Yi; Myoungsub Kim; Jungwon Seo; Namkyun Park; Seungyun Lee; Jongil Kim; Gapsok Do; Hongjin Jang; Hyochol Koo; Sunglae Cho; Sujin Chae; Taehoon Kim; et al. (VLSI Technology and Circuits, 2023)

The Compact Support Property for Solutions to the Stochastic Partial Differential Equations with Colored Noise. - Beom Seok Han; Kunwoo Kim; Jaeyun Yi (SIAM J. Math. Anal., 2023)

Realistic Noise-aware Training as a Component of the Holistic ACiM Development Platform. - Jihun Kim; Sangsu Park; Hongju Suh; Youngjae Kwon; Seonghun Lee; Yubin Lee; Kayoung Kim; Eungu Han; Jongil Kim; Kyu Sung Kim; Hyejung Choi; Seungwook Ryu; et al. (IMW, 2024)

Modeling and Demonstration for Multi-level Weight Conductance in Computational FeFET Memory Cell. - Won-Tae Koo; Jae-Gil Lee; Gunhee Lee; Woocheol Lee; Jungwook Woo; Dong Ik Suh; Joongsik Kim; Hyung Dong Lee; Seho Lee; Jaeyun Yi; Seonyong Cha (IMW, 2024)

Improvement of MAC Accuracy using Oxygen Diffusion Barriers in Resistive Synaptic Cell Arrays. - Youngjae Kwon; Won-Tae Koo; Sangsu Park; Dong Ik Suh; Gunhee Lee; Hyung Dong Lee; Youngbae Ahn; Dohee Kim; Seungwook Ryu; Hoseok Em; Seokjoon Kang; Chang Won Jeong; et al. (IMW, 2024)

First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory. - Myoungsub Kim; Yooncheol Bae; Jaehyuk Park; Jeongho Yeon; Hyungjoon Shim; Sehyun Jin; Hyunsoo Kim; Sangchul Oh; Gapsok Do; Dongyeol Yun; Hyung Dong Lee; David Ahn; et al. (VLSI Technology and Circuits, 2024)