A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems. - Jagdeep Kaur Sahani; Anil Singh; Alpana Agarwal (IntelliSys (1), 2019)

A 2.3 mW Multi-Frequency Clock Generator with -137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology. - Jagdeep Kaur Sahani; Anil Singh; Alpana Agarwal (J. Circuits Syst. Comput., 2020)

A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology. - Jagdeep Kaur Sahani; Anil Singh; Alpana Agarwal (J. Circuits Syst. Comput., 2020)

A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS. - Jagdeep Kaur Sahani; Anil Singh; Alpana Agarwal (Circuits Syst. Signal Process., 2022)

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator. - Jagdeep Kaur Sahani; Anil Singh; Alpana Agarwal (Int. J. Circuit Theory Appl., 2022)