A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. - Avinash K. Gautam; Jagdish C. Rao; Karthikeyan Madathil; Vilesh Shah; H. Udayakumar; Amitabh Menon; Subash Chandar G. (ICCD, 1999)

A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. - Avinash K. Gautam; Jagdish C. Rao; Rohit Rathi; H. Udayakumar (VLSI Design, 1999)

A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. - Karthikeyan Madathil; Jagdish C. Rao; Subash Chandar G.; Amitabh Menon; Avinash K. Gautam; Amit M. Brahme; H. Udayakumar (VLSI Design, 2000)

Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. - Karanth Shankaranarayana; Soujanna Sarkar; R. Venkatraman; Shyam S. Jagini; N. Venkatesh; Jagdish C. Rao; H. Udayakumar; M. Sambandam; K. P. Sheshadri; S. Talapatra; Parag Mhatre; Jais Abraham; et al. (ASP-DAC/VLSI Design, 2002)

Enabling Quality and Schedule Predictability in SoC Design using HandoffQC. - Bhaskar J. Karmakar; V. Kalyana Chakravarty; R. Venkatraman; Jagdish C. Rao (ISQED, 2006)

Clock gating for power optimization in ASIC design cycle theory & practice. - Sukumar Jairam; Madhusudan Rao; Jithendra Srinivas; Parimala Vishwanath; H. Udayakumar; Jagdish C. Rao (ISLPED, 2008)

Clock gating effectiveness metrics: Applications to power optimization. - Jithendra Srinivas; Madhusudan Rao; Sukumar Jairam; H. Udayakumar; Jagdish C. Rao (ISQED, 2009)

Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions. - R. Venkatraman; Shrikrishna Pundoor; Arun Koithyar; Madhusudan Rao; Jagdish C. Rao (VLSI Design, 2009)