Architectures and algorithms for image and video processing using FPGA-based platform. - Jai Gopal Pandey; Arindam Karmakar; S. Gurunarayanan 001 (VDAT, 2014)

A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm. - Jai Gopal Pandey; Arindam Karmakar; Chandra Shekhar 001; S. Gurunarayanan 001 (VLSID, 2014)

An embedded framework for accurate object localization using center of gravity measure with mean shift procedure. - Jai Gopal Pandey; Arindam Karmakar; Chandra Shekhar 001; S. Gurunarayanan 001 (VDAT, 2015)

An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications. - Jai Gopal Pandey; Arindam Karmakar; Chandra Shekhar 001; S. Gurunarayanan 001 (VLSID, 2015)

An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation. - Jai Gopal Pandey; Tarun Goel; Abhijit Karmakar (VDAT, 2017)

A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCs. - Jai Gopal Pandey; Tarun Goel; Mausam Nayak; Chhavi Mitharwal; Abhijit Karmakar; Raj Singh (SoCC, 2018)

A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations. - Jai Gopal Pandey; Tarun Goel; Mausam Nayak; Chhavi Mitharwal; Sajid Khan 001; Santosh Kumar Vishvakarma; Abhijit Karmakar; Raj Singh (VDAT, 2018)

A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher. - Jai Gopal Pandey; Tarun Goel; Abhijit Karmakar (VLSID, 2018)

An RNS Implementation of the Elliptic Curve Cryptography for IoT Security. - Jai Gopal Pandey; Chhavi Mitharwal; Abhijit Karmakar (TPS-ISA, 2019)

An Ultra Low Power AES Architecture for IoT. - Sajid Khan 001; Neha Gupta; Gopal Raut; Gunjan Rajput; Jai Gopal Pandey; Santosh Kumar Vishvakarma (VDAT, 2019)

Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. - Sajid Khan 001; Neha Gupta; Abhinav Vishwakarma; Shailesh Singh Chouhan; Jai Gopal Pandey; Santosh Kumar Vishvakarma (VDAT, 2019)

A Novel Design of SRAM Using Memristors at 45 nm Technology. - Victor Jeffry Louis; Jai Gopal Pandey (VDAT, 2019)

Hardware architectures for PRESENT block cipher and their FPGA implementations. - Jai Gopal Pandey; Tarun Goel; Abhijit Karmakar (IET Circuits Devices Syst., 2019)

An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications. - Sajid Khan 001; Ambika Prasad Shah; Neha Gupta; Shailesh Singh Chouhan; Jai Gopal Pandey; Santosh Kumar Vishvakarma (Microelectron. J., 2019)

A Unified Architecture for AES/PRESENT Ciphers and its Usage in an SoC Environment. - Jai Gopal Pandey; Sanskriti Gupta; Abhijit Karmakar (LASCAS, 2020)

A Lightweight VLSI Architecture for RECTANGLE Cipher and its Implementation on an FPGA. - Jai Gopal Pandey; Ayush Laddha; Sashwat Deb Samaddar (VDAT, 2020)

A Highly Stable and Robust 7T SRAM Cell using Memristor. - Sahan Panguluru; Jai Gopal Pandey (VDAT, 2020)

A Hardware Generator for Posit Arithmetic and its FPGA Prototyping. - Diksha Shekhawat; Apoorva Jangir; Jai Gopal Pandey (VDAT, 2021)

An embedded FPGA-SoC framework and its usage in moving object tracking application. - Jai Gopal Pandey (Des. Autom. Embed. Syst., 2021)

GIFT cipher usage in image data security: hardware implementations, performance and statistical analyses. - Apoorva Jangir; Jai Gopal Pandey (J. Real Time Image Process., 2021)

An Overlap-and-Add Based Time Domain Acceleration of CNNs on FPGA-CPU Systems. - Rudresh Pratap Singh; Shreyam Kumar; Jai Gopal Pandey (VDAT, 2022)

LOKI: A Secure FPGA Prototyping of IoT IP with Lightweight Logic Locking. - Jugal Gandhi; Diksha Shekhawat; M. Santosh; Jai Gopal Pandey (APCCAS, 2023)

PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations. - Diksha Shekhawat; Jugal Gandhi; M. Santosh; Jai Gopal Pandey (CoNGA, 2023)

Security Evaluation of Lightweight SBoxes. - Jugal Gandhi; Diksha Shekhawat; M. Santosh; Jai Gopal Pandey (iSES, 2023)

An RTL Implementation of the Data Encryption Standard (DES). - Ruby Kumari; Jai Gopal Pandey; Abhijit Karmakar (CoRR, 2023)

Logic locking for IP security: A comprehensive analysis on challenges, techniques, and trends. - Jugal Gandhi; Diksha Shekhawat; M. Santosh; Jai Gopal Pandey (Comput. Secur., 2023)

Large Language Model Driven Logic Locking: A Generative Approach to Secure IC Design. - Jugal Gandhi; Diksha Shekhawat; M. Santosh; Jaya Dofe; Jai Gopal Pandey (ATS, 2024)

Emerging Frontiers and Limitations of Logic Locking for Secure IC Design. - Jugal Gandhi; Diksha Shekhawat; M. Santosh; Jai Gopal Pandey (MCSoC, 2024)

Security Assessment of Rotation Countermeasure for Protection Against Fault Attacks. - Maitri Iyer; Rishav Bhowmick; Harsh Singh; Jai Gopal Pandey (VDAT, 2024)

Design and Analysis of an Area and Power Efficient Programmable Delay Cell. - Kuntal Chakraborty; Jai Gopal Pandey; Abir J. Mondal (VLSID, 2024)

SAT and SCOPE Attacks on Deceptive Multiplexer Logic Locking. - Jugal Gandhi; Rishi Agarwal; Anish Mall; Diksha Shekhawat; M. Santosh; Jai Gopal Pandey (VLSID, 2024)

Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher. - Kartik Jhawar; Jugal Gandhi; Diksha Shekhawat; Aniket Upadhyay; Avadh Harkishanka; Nitin Chaturvedi; M. Santosh; Jai Gopal Pandey (J. Real Time Image Process., 2024)

DyLock: A Dynamic Key-based SAT and Structural Attacks Resilient Low-overhead Logic Locking. - Jugal Gandhi; Diksha Shekhawat; Jaya Dofe; Jai Gopal Pandey (ISCAS, 2025)

SHAKTI: Securing Hardware IPs by Cascade Gated Multiplexer-Based Logic Obfuscation. - Jugal Gandhi; Nikhil Handa; Abhay Nayak; Diksha Shekhawat; M. Santosh; Jaya Dofe; Jai Gopal Pandey (VLSID, 2025)

An Efficient Hardware Implementation of Elliptic Curve Point Multiplication over GF(2m) on FPGA. - Ruby Kumari; Tapas Rout; Babul Saini; Jai Gopal Pandey; Abhijit Karmakar (CoRR, 2025)