A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth. - Jei-Hwan Yoo; Chang-Hyun Kim; Kyu-Chan Lee; Kye-Hyun Kyung; Seung-Moon Yoo; Jung-Hwa Lee; Moon-Hae Son; Jin-Man Han; Bok-Moon Kang; Ejaz Haq; Sang-Bo Lee; Jai-Hoon Sim; et al. (IEEE J. Solid State Circuits, 1996)

Low-voltage, high-speed circuit designs for gigabit DRAMs. - Kyu-Chan Lee; Changhyun Kim; Dong-Ryul Ryu; Jai-Hoon Sim; Sang-Bo Lee; Byung-Sik Moon; Keum-Yong Kim; Nam-Jong Kim; Seung-Moon Yoo; Hongil Yoon; Jei-Hwan Yoo; Soo-In Cho (IEEE J. Solid State Circuits, 1997)