Graph matching-based algorithms for FPGA segmentation design. - Yao-Wen Chang; Jai-Ming Lin; D. F. Wong 001 (ICCAD, 1998)

TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. - Jai-Ming Lin; Yao-Wen Chang (DAC, 2001)

An Algorithm for Dynamically Reconfigurable FPGA Placement. - Guang-Ming Wu; Jai-Ming Lin; Yao-Wen Chang (ICCD, 2001)

Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. - Guang-Ming Wu; Jai-Ming Lin; Mango Chia-Tso Chao; Yao-Wen Chang (ICCD, 2001)

Matching-based algorithm for FPGA channel segmentation design. - Yao-Wen Chang; Jai-Ming Lin; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Generic ILP-based approaches for time-multiplexed FPGA partitioning. - Guang-Ming Wu; Jai-Ming Lin; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. - Jai-Ming Lin; Hsin-Lung Chen; Yao-Wen Chang (DATE, 2002)

Performance-driven placement for dynamically reconfigurable FPGAs. - Guang-Ming Wu; Jai-Ming Lin; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2002)

Arbitrarily shaped rectilinear module placement using the transitive closure graph representation. - Jai-Ming Lin; Hsin-Lung Chen; Yao-Wen Chang (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Graph matching-based algorithms for array-based FPGA segmentation design and routing. - Jai-Ming Lin; Song-Ra Pan; Yao-Wen Chang (ASP-DAC, 2003)

Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. - Jai-Ming Lin; Yao-Wen Chang; Shih-Ping Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 2003)

TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. - Jai-Ming Lin; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Placement with symmetry constraints for analog layout design using TCG-S. - Jai-Ming Lin; Guang-Ming Wu; Yao-Wen Chang; Jen-Hui Chuang (ASP-DAC, 2005)

TCG: A transitive closure graph-based representation for general floorplans. - Jai-Ming Lin; Yao-Wen Chang (IEEE Trans. Very Large Scale Integr. Syst., 2005)

UFO: unified convex optimization algorithms for fixed-outline floorplanning. - Jai-Ming Lin; Hsi Hung (ASP-DAC, 2010)

Performance-driven analog placement considering boundary constraint. - Cheng-Wu Lin; Jai-Ming Lin; Chun-Po Huang; Soon-Jyh Chang (DAC, 2010)

Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction. - Jia-Ru Chuang; Jai-Ming Lin (ASP-DAC, 2011)

Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. - Cheng-Wu Lin; Jai-Ming Lin; Yen-Chih Chiu; Chun-Po Huang; Soon-Jyh Chang (DAC, 2011)

UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules. - Jai-Ming Lin; Zhi-Xiong Hung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Voltage island-driven floorplanning considering level shifter placement. - Jai-Ming Lin; Wei-Yi Cheng; Chung-Lin Lee; Richard C. Hsu (ASP-DAC, 2012)

Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits. - Cheng-Wu Lin; Chung-Lin Lee; Jai-Ming Lin; Soon-Jyh Chang (ICCAD, 2012)

Routability-driven placement algorithm for analog integrated circuits. - Cheng-Wu Lin; Cheng-Chung Lu; Jai-Ming Lin; Soon-Jyh Chang (ISPD, 2012)

Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors. - Cheng-Wu Lin; Jai-Ming Lin; Yen-Chih Chiu; Chun-Po Huang; Soon-Jyh Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems. - Jai-Ming Lin; Zhi-Xiong Hung (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. - Ya-Ting Shyu; Jai-Ming Lin; Chun-Po Huang; Cheng-Wu Lin; Ying-Zu Lin; Soon-Jyh Chang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Current density aware power switch placement algorithm for power gating designs. - Jai-Ming Lin; Che-Chun Lin; Zong-Wei Syu; Chih-Chung Tsai; Kevin Huang (ISPD, 2014)

F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint. - Jai-Ming Lin; Ji-Heng Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint. - Jai-Ming Lin; Chih-Yao Hu; Kai-Chung Chan (VLSI-DAT, 2015)

Placement Density Aware Power Switch Planning Methodology for Power Gating Designs. - Jai-Ming Lin; Che-Chun Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. - Liang-Ying Lu; Ching-Yao Chang; Zhao-Hong Chen; Bo-Ting Yeh; Tai-Hua Lu; Peng-Yu Chen; Pin-Hao Tang; Kuen-Jong Lee; Lih-Yih Chiou; Soon-Jyh Chang; Chien-Hung Tsai; Chung-Ho Chen; et al. (ASP-DAC, 2016)

SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs. - Jai-Ming Lin; Po-Yang Chiu; Yen-Fu Chang (ICCAD, 2016)

An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs. - Ya-Ting Shyu; Jai-Ming Lin; Che-Chun Lin; Chun-Po Huang; Soon-Jyh Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A Systematic Design Methodology of Asynchronous SAR ADCs. - Chun-Po Huang; Jai-Ming Lin; Ya-Ting Shyu; Soon-Jyh Chang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits. - Jai-Ming Lin; Bo-Heng Yu; Li-Yen Chang (ASP-DAC, 2017)

Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs. - Jai-Ming Lin; Jung-An Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

General floorplanning methodology for 3D ICs with an arbitrary bonding style. - Jai-Ming Lin; Chien-Yu Huang (DATE, 2018)

Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs. - Jai-Ming Lin; Chien-Yu Huang; Jhih-Ying Yang (DATE, 2018)

A fast thermal-aware fixed-outline floorplanning methodology based on analytical models. - Jai-Ming Lin; Tai-Ting Chen; Yen-Fu Chang; Wei-Yi Chang; Ya-Ting Shyu; Yeong-Jar Chang; Juin-Ming Lu (ICCAD, 2018)

Macro-aware row-style power delivery network design for better routability. - Jai-Ming Lin; Jhih-Sheng Syu; I-Ru Chen (ICCAD, 2018)

Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros. - Jai-Ming Lin; Szu-Ting Li; Yi-Ting Wang (DAC, 2019)

A Novel Macro Placement Approach based on Simulated Evolution Algorithm. - Jai-Ming Lin; You-Lun Deng; Ya-Chu Yang; Jia-Jian Chen; Yao-Chieh Chen (ICCAD, 2019)

Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles. - Jai-Ming Lin; You-Lun Deng; Szu-Ting Li; Bo-Heng Yu; Li-Yen Chang; Te-Wei Peng (IEEE Trans. Very Large Scale Integr. Syst., 2019)

DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs. - Jai-Ming Lin; Wei-Fan Huang; Yao-Chieh Chen; Yi-Ting Wang; Po-Wen Wang (ICCAD, 2021)

Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs. - Jai-Ming Lin; Chung-Wei Huang; Liang-Chi Zane; Min-Chia Tsai; Che-Li Lin; Chen-Fa Tsai (ICCAD, 2021)

A Fast Power Network Optimization Algorithm for Improving Dynamic IR-drop. - Jai-Ming Lin; Yang-Tai Kung; Zheng-Yu Huang; I-Ru Chen (ISPD, 2021)

Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation. - Jai-Ming Lin; Tai-Ting Chen; Hao-Yuan Hsieh; Ya-Ting Shyu; Yeong-Jar Chang; Juin-Ming Lu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC. - Jai-Ming Lin; Wei-Yi Chang; Hao-Yuan Hsieh; Ya-Ting Shyu; Yeong-Jar Chang; Juin-Ming Lu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs. - Jai-Ming Lin; You-Lun Deng; Ya-Chu Yang; Jia-Jian Chen; Po-Chen Lu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs. - Jai-Ming Lin; Hao-Yuan Hsieh; Hsuan Kung; Hao-Jia Lin (ICCAD, 2022)

A Novel Blockage-Avoiding Macro Placement Approach for 3D ICs Based on POCS. - Jai-Ming Lin; Po-Chen Lu; Heng-Yu Lin; Jia-Ting Tsai (ICCAD, 2022)

PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability. - Jai-Ming Lin; Liang-Chi Zane; Min-Chia Tsai; Yung-Chen Chen; Che-Li Lin; Chen-Fa Tsai (IEEE Trans. Very Large Scale Integr. Syst., 2022)

HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique. - Jai-Ming Lin; Yu-Chien Lin; Hsuan Kung; Wei-Yuan Lin (ICCAD, 2023)

Routability-Driven Orientation-Aware Analytical Placement for System in Package. - Jai-Ming Lin; Tsung-Chun Tsai; Rui-Ting Shen (ICCAD, 2023)

Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery Network. - Jai-Ming Lin; Yu-Tien Chen; Yang-Tai Kung; Hao-Jia Lin (ISPD, 2023)

Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in Package. - Jai-Ming Lin; Tsung-Lin Tsai; Tsung-Chun Tsai (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An Effective Analytical Placement Approach to Handle Fence Region Constraint. - Jai-Ming Lin; Wei-Yuan Lin; Yung-Chen Chen; Pin-Yu Chen; Chen-Fa Tsai; De-Shiun Fu; Che-Li Lin (ICCAD, 2024)

Timing-Driven Analytical Placement According to Expected Cell Distribution Range. - Jai-Ming Lin; You-Yu Chang; Wei-Lun Huang (ISPD, 2024)

Effective Macro Placement for Very Large Scale Designs Using MCTS Guided by Pre-Trained RL. - Jai-Ming Lin; Zong-Ze Lee; Nan-Chu Lin (DATE, 2025)

IR-drop Aware Power Network Synthesis for Power Gating Designs. - Jai-Ming Lin; Hsin-Lin Chen (ACM Great Lakes Symposium on VLSI, 2025)

An Effective Voltage-drop Aware Analytical Placement Approach. - Jai-Ming Lin; Pin-Yu Chen; Min-Chia Tsai; Chen-Fa Tsai; De-Shiun Fu; Che-Li Lin (ACM Great Lakes Symposium on VLSI, 2025)