Improvement of GIDL-assisted Erase by using Surrounded BL PAD Structure for VNAND. - Suhwan Lim; Samki Kim; Changhee Lee; Hyeongwon Choi; Nambin Kim; Jaehun Jung; Hanvit Yang; Tae-Hun Kim; Junhee Lim; Daewon Ha; Sunghoi Hur; Jae-hoon Jang; et al. (IMW, 2023)

Trends and Future Challenges of 3D NAND Flash Memory. - Sun Il Shim; Jaehoon Jang 002; Jaihyuk Song (IMW, 2023)

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET. - Taeyoung Kim; Suhwan Lim; Ilho Myeong; Sanghyun Park; Suseong Noh; Seung Min Lee; Jongho Woo; Hanseung Ko; Youngji Noh; Moonkang Choi; Kiheun Lee; Sangwoo Han; et al. (IRPS, 2024)

A Novel Quantitative Model for Combination Effects of Hydrogen and Process Heat on Peripheral Transistors in 3D-NAND Flash Memory. - Dongjin Lee; Yunjo Lee; Soyeong Na; KangOh Yun; Sungkweon Baek; Jaeduk Lee; Jaehoon Jang 002; Jaihyuk Song (IRPS, 2024)

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND. - Ilho Myeong; Suhwan Lim; Taeyoung Kim; Sanghyun Park; Suseong Noh; Seung Min Lee; Jongho Woo; Hanseung Ko; Youngji Noh; Munkang Choi; Kiheun Lee; Sangwoo Han; et al. (IRPS, 2024)

6.10 A 1/1.56-inch 50Mpixel CMOS Image Sensor with 0.5μm pitch Quad Photodiode Separated by Front Deep Trench Isolation. - DongHyun Kim; Kwansik Cho; Ho-Chul Ji; Minkyung Kim 010; Junghye Kim; Taehoon Kim; Seungju Seo; Dongmo Im; You-Na Lee 001; Jinyong Choi; Sunghyun Yoon; Inho Noh; et al. (ISSCC, 2024)

Expanding Design Technology Co-Optimization Potentials with Back-Side Interconnect Innovation. - Byung-Sung Kim; Subin Choi; Jung Han Lee; Kwangmuk Lee; Jisoo Park; Jiwook Kwon; Saehan Park; Kwanyoung Chun; Harsono Simka; Aravindh Kumar; Muhammed Ahosan Ul Karim; Ken Rim; et al. (VLSI Technology and Circuits, 2024)

A Metal Dual Work-Function Gate (MDWG) for the Continuous Scaling of DRAM Cell Transistors. - Junsoo Kim; Hyun Jung Lee; Sung Ho Jang; Jun Bum Lee; Ilgweon Kim; Jeonghoon Oh; Jemin Park; Jaihyuk Song (VLSI Technology and Circuits, 2024)

Cell to Core-Periphery Overlap (C2O) Based on BCAT for Next Generation DRAM. - Kiseok Lee; Hongjun Lee; Hyungeun Choi; Jeongsu Kim; Kyunghwan Kim; Moonyoung Jeong; Soohyun Bae; Hyebin Kim; Jiyun Lee; Minsoo Kim; Keunnam Kim; Huijung Kim; et al. (VLSI Technology and Circuits, 2024)

Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch. - Jaehyun Park; Juhun Park; Kyuman Hwang; Jinchan Yun; Dahye Kim; Sungil Park; Jejune Park; Jinwook Yang; Jae Won Jeong; Chuljin Yun; Jinho Bae; Sam Park; et al. (VLSI Technology and Circuits, 2024)

Future Technology Outlook on DRAM/Flash Memories for More Moore and More Than Moore. - Su-Jin Ahn; Young Guen Song; Dongguk Cho; Daewon Ha; Wanki Kim; Kwangmin Park; Kwangjin Moon; Jin-Woo Han; Seon Il Shim; Sangjin Hyun; Jaihyuk Song (IMW, 2025)

A Study on the Origin of Dynamic Charge Loss of Next Generation DRAM Cell Array Transistor. - Moonyoung Jeong; Hyungjun Noh; Sangho Lee; Yootak Jun; Jeonghoon Oh; Jemin Park; Jaihyuk Song (IRPS, 2025)

6.1 A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2µm -Pitch 50Mpixel Rolling Shutter and 2.4µm -Pitch 12.5Mpixel Global Shutter Modes for Mobile Applications. - Heesung Shim; Seung Sik Kim; Min-Woong Seo; Sangsu Park; Hyukbin Kwon; Yongjun Kim; Sanggwon Lee; Sungbong Park; Daehee Bae; Si Gyoung Koo; Masamichi Ito; Jae-hoon Jeon; et al. (ISSCC, 2025)

AI Revolution Driven by Memory Technology Innovation. - Jaihyuk Song (ISSCC, 2025)