On the development of a SISCO implementation using Java. - Jaime Espinosa; José A. Pino; Patricia Pollard (CRIWG, 1997)

Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environments. - Jaime Espinosa; David de Andrés; Juan Carlos Ruiz 001; Pedro J. Gil (FPL, 2012)

The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs. - Jaime Espinosa; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (EWDC, 2013)

Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification. - Jaime Espinosa; Carles Hernández 001; Jaume Abella 001; David de Andrés; Juan-Carlos Ruiz-Garcia 001 (DAC, 2015)

Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults. - Jaime Espinosa; David de Andrés; Pedro J. Gil (EDCC, 2015)

Characterizing fault propagation in safety-critical processor designs. - Jaime Espinosa; Carles Hernández 001; Jaume Abella 001 (IOLTS, 2015)

Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection. - Jaime Espinosa; Carles Hernández 001; Jaume Abella 001 (IOLTS, 2016)