Replication and Pipelining in Multiple-Instance Algorithms. - Jaime H. Moreno; Tomás Lang (ICPP, 1986)

Graph-based Partitioning of Matrix Algorithms for Systolic Arrays: Application to Transitive Closure. - Jaime H. Moreno; Tomás Lang (ICPP (1), 1988)

Comments on 'A systolic array for computing BA-1'. - Jaime H. Moreno; Tomás Lang (IEEE Trans. Acoust. Speech Signal Process., 1989)

A graph-based approach to map matrix algorithms onto local-access processor arrays. - Jaime H. Moreno; Tomás Lang (ASAP, 1990)

Matrix Computations on Systolic-Type Meshes. - Jaime H. Moreno; Tomás Lang (Computer, 1990)

A decoupled access/execute processor for matrix algorithms: architecture and programming. - Jaime H. Moreno; Miguel E. Figueroa (ASAP, 1991)

Linear pseudosystolic array for partitioned matrix algorithms. - Jaime H. Moreno; Miguel E. Figueroa; Tomás Lang (J. VLSI Signal Process., 1991)

MAMACG: a tool for automatic mapping of matrix algorithms onto mesh array computational graphs. - Dinh Lê; Milos D. Ercegovac; Tomás Lang; Jaime H. Moreno (ASAP, 1992)

Introduction. - Tomás Lang; Jaime H. Moreno (J. VLSI Signal Process., 1993)

Scalable Instruction-Level Parallelism Through Tree-Instructions. - Jaime H. Moreno; Mayan Moudgill (International Conference on Supercomputing, 1997)

Simulation/evaluation environment for a VLIW processor architecture. - Jaime H. Moreno; Mayan Moudgill; Kemal Ebcioglu; Erik R. Altman; C. Brian Hall; Rene Miranda; Shyh-Kwei Chen; Arkady Polyak (IBM J. Res. Dev., 1997)

Validation of Turandot, a fast processor model for microarchitecture exploration. - Mayan Moudgill; Pradip Bose; Jaime H. Moreno (IPCCC, 1999)

Environment for PowerPC microarchitecture exploration. - Mayan Moudgill; John-David Wellman; Jaime H. Moreno (IEEE Micro, 1999)

A new look at exploiting data parallelism in embedded systems. - Hillery C. Hunter; Jaime H. Moreno (CASES, 2003)

A high-performance embedded DSP core with novel SIMD features. - Jeff H. Derby; Jaime H. Moreno (ICASSP (2), 2003)

Reducing instruction fetch energy with backwards branch control information and buffering. - Jude A. Rivers; Sameh W. Asaad; John-David Wellman; Jaime H. Moreno (ISLPED, 2003)

An innovative low-power high-performance programmable signal processor for digital communications. - Jaime H. Moreno; Victor V. Zyuban; Uzi Shvadron; Fredy D. Neeser; Jeff H. Derby; Malcolm S. Ware; Krishnan Kailas; Ayal Zaks; Amir B. Geva; Shay Ben-David; Sameh W. Asaad; Thomas W. Fox; et al. (IBM J. Res. Dev., 2003)

Design methodology for semi custom processor cores. - Victor V. Zyuban; Sameh W. Asaad; Thomas W. Fox; Anne-Marie Haen; Daniel Littrell; Jaime H. Moreno (ACM Great Lakes Symposium on VLSI, 2004)

Chip-level integration: the new frontier for microprocessor architecture. - Jaime H. Moreno (SPAA, 2006)

True value: assessing and optimizing the cost of computing at the data center level. - John P. Karidis; José E. Moreira; Jaime H. Moreno (Conf. Computing Frontiers, 2009)

Extreme scale computing: Challenges and opportunities. - Josep Torrellas; Bill Gropp; Vivek Sarkar; Jaime H. Moreno; Kunle Olukotun (HPCA, 2010)

3D stacking of high-performance processors. - Philip G. Emma; Alper Buyuktosunoglu; Michael B. Healy; Krishnan Kailas; Valentin Puente; Roy Yu; Allan Hartstein; Pradip Bose; Jaime H. Moreno; Eren Kursun (HPCA, 2014)

Near-Data Processing: Insights from a MICRO-46 Workshop. - Rajeev Balasubramonian; Jichuan Chang; Troy Manning; Jaime H. Moreno; Richard Murphy; Ravi Nair; Steven Swanson (IEEE Micro, 2014)

Active Memory Cube: A processing-in-memory architecture for exascale systems. - Ravi Nair; Samuel Antão; Carlo Bertolli; Pradip Bose; José R. Brunheroto; Tong Chen 001; Chen-Yong Cher; Carlos H. A. Costa; J. Doi; Constantinos Evangelinos; Bruce M. Fleischer; Thomas W. Fox; et al. (IBM J. Res. Dev., 2015)

Near-Memory Data Services. - Babak Falsafi; Mircea Stan; Kevin Skadron; Nuwan Jayasena; Yunji Chen; Jinhua Tao; Ravi Nair; Jaime H. Moreno; Naveen Muralimanohar; Karthikeyan Sankaralingam; Cristian Estan (IEEE Micro, 2016)

Benchmarking Summit and Sierra Supercomputers : From Proposal to Acceptance. - Jaime H. Moreno; Hui-Fang Wen (HPCS, 2019)

Preparation and optimization of a diverse workload for a large-scale heterogeneous system. - Ian Karlin; Yoonho Park; Bronis R. de Supinski; Peng Wang; Bert Still; David Beckingsale; Robert Blake; Tong Chen 001; Guojing Cong; Carlos H. A. Costa; Johann Dahm; Giacomo Domeniconi; et al. (SC, 2019)