A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx. - Jais Abraham; Narayan Prasad; Srinivasa Chakravarthy B. S.; Ameet Bagwe; Rubin A. Parekhji (ITC, 2000)

Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. - Karanth Shankaranarayana; Soujanna Sarkar; R. Venkatraman; Shyam S. Jagini; N. Venkatesh; Jagdish C. Rao; H. Udayakumar; M. Sambandam; K. P. Sheshadri; S. Talapatra; Parag Mhatre; Jais Abraham; et al. (ASP-DAC/VLSI Design, 2002)

Multi-Cycle Sensitizable Transition Delay Faults. - Jais Abraham; Uday Goel; Arun Kumar (VTS, 2006)

Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. - Sandeep Jain; Jais Abraham; Srinivas Kumar Vooka; Sumant Kale; Amit Dutta; Rubin A. Parekhji (VLSI Design, 2007)

Evaluation of Entropy Driven Compression Bounds on Industrial Designs. - Srinivasulu Alampally; Jais Abraham; Rubin A. Parekhji; Rohit Kapur; Thomas W. Williams (ATS, 2008)

Test Time Minimisation in Scan Compression Designs Using Dynamic Channel Allocation. - Jais Abraham; Shankar Umapathi; Sumitha Krishnamurthi (VLSID, 2016)

Adapting an industrial memory BIST solution for testing CAMs. - Jais Abraham; Uttam Garg; Glenn Colón-Bonet; Ramesh Sharma; Chennian Di; Benoit Nadeau-Dostie; Etienne Racine; Martin Keim (ITC-Asia, 2017)

Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test. - Ankush Srivastava; Jais Abraham (ITC, 2022)

Revisiting Test Compression Configuration in Context of Multi-Core Testing Using Packetized Scan Network. - Subhadip Kundu; Jais Abraham (VLSID, 2024)