Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. - Jakub Cabal; Pavel Benácek; Lukas Kekely; Michal Kekely; Viktor Pus; Jan Korenek (FPGA, 2018)

High-Speed Computation of CRC Codes for FPGAs. - Jakub Cabal; Lukás Kekely; Jan Korenek (FPT, 2018)

Effective FPGA Architecture for General CRC. - Lukás Kekely; Jakub Cabal; Jan Korenek (ARCS, 2019)

Scalable P4 Deparser for Speeds Over 100 Gbps. - Jakub Cabal; Pavel Benácek; Jana Foltova; Juraj Holub (FCCM, 2019)

Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. - Lukás Kekely; Jakub Cabal; Viktor Pus; Jan Korenek (DSD, 2020)

DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers. - Jan Kubálek; Jakub Cabal; Martin Spinler; Radek Isa (FCCM, 2021)

FPL Demo: 400G FPGA Packet Capture Based on Network Development Kit. - Jakub Cabal; Jiri Sikora; Stepán Friedl; Martin Spinler; Jan Korenek (FPL, 2022)

400G Ethernet Packet Capture Demo Based on Network Development Kit for FPGAs. - Jakub Cabal; Vladislav Válek; Martin Spinler; Daniel Kondys; Jan Korenek (INFOCOM Workshops, 2023)