Dynamic channel allocation for higher EDT compression in SoC designs. - Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jakub Janicki; Jerzy Tyszer (ITC, 2010)

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Jakub Janicki (Asian Test Symposium, 2011)

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. - Jakub Janicki; Jerzy Tyszer; Avijit Dutta; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2011)

Bandwidth-aware test compression logic for SoC designs. - Jakub Janicki; Jerzy Tyszer; Grzegorz Mrugalski; Janusz Rajski (ETS, 2012)

EDT Bandwidth Management in SoC Designs. - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

EDT bandwidth management - Practical scenarios for large SoC designs. - Jakub Janicki; Jerzy Tyszer; Wu-Tung Cheng; Yu Huang 005; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski; Yan Dong; Grady Giles (ITC, 2013)

Test Time Reduction in EDT Bandwidth Management for SoC Designs. - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. - Maciej Trawka; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jakub Janicki; Jerzy Tyszer (ATS, 2014)

Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. - Wu-Tung Cheng; Yan Dong; Grady Giles; Yu Huang 005; Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution. - Yu Huang 005; Jakub Janicki; Szczepan Urban (ETS, 2019)

Scan Chain Diagnosis-Driven Test Response Compactor. - Jakub Janicki; Grzegorz Mrugalski; Artur Stelmach; Szczepan Urban (ATS, 2020)

Industry Evaluation of Reversible Scan Chain Diagnosis. - Soumya Mittal; Szczepan Urban; Kun Young Chung; Jakub Janicki; Wu-Tung Cheng; Martin Parley; Manish Sharma; Shaun Nicholson (ITC, 2022)

Predicting the Resolution of Scan Diagnosis. - Manoj Devendhiran; Jakub Janicki; Szczepan Urban; Manish Sharma; Jayant D'Souza (ITC, 2023)

Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage. - Wu-Tung Cheng; Manish Sharma; Xin Yang; Artur Stelmach; Szczepan Urban; Jakub Janicki; Preston McWithey (ITC, 2024)