FPGA Prototyping and Accelerated Verification of ASIPs. - Jakub Podivinsky; Marcela Simková; Ondrej Cekan; Zdenek Kotásek (DDECS, 2015)

Software Fault Tolerance: The Evaluation by Functional Verification. - Ondrej Cekan; Jakub Podivinsky; Zdenek Kotásek (DSD, 2015)

The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applications. - Jakub Podivinsky; Ondrej Cekan; Marcela Simková; Zdenek Kotásek (Microprocess. Microsystems, 2015)

Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems. - Jakub Podivinsky; Ondrej Cekan; Jakub Lojda; Zdenek Kotásek (DSD, 2016)

Random stimuli generation based on a stochastic context-free grammar. - Ondrej Cekan; Jakub Podivinsky; Zdenek Kotásek (FPT, 2016)

HLS-based fault tolerance approach for SRAM-based FPGAs. - Jakub Lojda; Jakub Podivinsky; Martin Krcma; Zdenek Kotásek (FPT, 2016)

Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs. - Jakub Podivinsky; Ondrej Cekan; Jakub Lojda; Zdenek Kotásek (FPT, 2016)

Reliability Analysis and Improvement of FPGA-Based Robot Controller. - Jakub Podivinsky; Jakub Lojda; Ondrej Cekan; Richard Panek; Zdenek Kotásek (DSD, 2017)

Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluation. - Jakub Lojda; Jakub Podivinsky; Zdenek Kotásek (EWDTS, 2017)

Data types and operations modifications: A practical approach to fault tolerance in HLS. - Jakub Lojda; Jakub Podivinsky; Zdenek Kotásek; Martin Krcma (EWDTS, 2017)

Functional verification based platform for evaluating fault tolerance properties. - Jakub Podivinsky; Ondrej Cekan; Jakub Lojda; Marcela Zachariásová; Martin Krcma; Zdenek Kotásek (Microprocess. Microsystems, 2017)

Program Generation Through a Probabilistic Constrained Grammar. - Ondrej Cekan; Jakub Podivinsky; Zdenek Kotásek (DSD, 2018)

FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. - Jakub Lojda; Jakub Podivinsky; Ondrej Cekan; Richard Panek; Zdenek Kotásek (DSD, 2018)

Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller. - Jakub Podivinsky; Jakub Lojda; Ondrej Cekan; Zdenek Kotásek (DSD, 2018)

Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. - Jakub Lojda; Jakub Podivinsky; Zdenek Kotásek (EWDTS, 2018)

Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. - Richard Panek; Jakub Lojda; Jakub Podivinsky; Zdenek Kotásek (EWDTS, 2018)

An Experimental Evaluation of Fault-Tolerant FPGA-Based Robot Controller. - Jakub Podivinsky; Jakub Lojda; Zdenek Kotásek (EWDTS, 2018)

Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. - Ondrej Cekan; Jakub Podivinsky; Jakub Lojda; Richard Panek; Martin Krcma; Zdenek Kotásek (DSD, 2019)

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. - Jakub Podivinsky; Ondrej Cekan; Martin Krcma; Radek Burget; Tomas Hruska; Zdenek Kotásek (DSD, 2019)

Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. - Jakub Lojda; Jakub Podivinsky; Zdenek Kotásek (LATS, 2019)

Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. - Jakub Podivinsky; Jakub Lojda; Zdenek Kotásek (LATS, 2019)

Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. - Jakub Lojda; Jakub Podivinsky; Ondrej Cekan; Richard Panek; Martin Krcma; Zdenek Kotásek (DDECS, 2020)

Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. - Jakub Lojda; Richard Panek; Jakub Podivinsky; Ondrej Cekan; Martin Krcma; Zdenek Kotásek (DSD, 2020)

Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. - Jakub Lojda; Richard Panek; Jakub Podivinsky; Ondrej Cekan; Martin Krcma; Zdenek Kotásek (EWDTS, 2020)

Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination. - Jakub Podivinsky; Ondrej Cekan; Martin Krcma; Radek Burget; Tomas Hruska; Zdenek Kotásek (LASCAS, 2020)

Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. - Jakub Podivinsky; Jakub Lojda; Richard Panek; Ondrej Cekan; Martin Krcma; Zdenek Kotásek (LASCAS, 2020)

Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. - Richard Panek; Jakub Lojda; Jakub Podivinsky; Zdenek Kotásek (VLSI-DAT, 2020)

Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. - Richard Panek; Jakub Lojda; Jakub Podivinsky; Zdenek Kotásek (DSD, 2021)

Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. - Jakub Lojda; Richard Panek; Jakub Podivinsky; Ondrej Cekan; Martin Krcma; Zdenek Kotásek (LATS, 2021)

Využití verifikace pro ověřování odolnosti proti poruchám u systémů založených na FPGA ; Use of verification for testing fault-tolerance in FPGA-based system. - Jakub Podivinsky (2024)