Competition stimulates technology advances: experiences from ADSL development in Japan. - Guozhu Long; Jalil Kamali; Amir H. Fazlollahi; Vinay R. Rao (IEEE Commun. Mag., 2005)

Design of high-speed wireline transceivers for backplane communications in 28nm CMOS. - Jafar Savoj; Kenny C.-H. Hsieh; Parag Upadhyaya; Fu-Tai An; Jay Im; Xuewen Jiang; Jalil Kamali; Kang Wei Lai; Zhaoyin Daniel Wu; Elad Alon; Ken Chang (CICC, 2012)

BER analysis of high speed links with nonlinearity. - Gaurav Malhotra; Jalil Kamali (ACSSC, 2015)

23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays. - Mohammad Hekmat; Sanquan Song; Nancy Jaffari; Sabarish Sankaranarayanan; Chaofeng Huang; Minghui Han; Gaurav Malhotra; Jalil Kamali; Amir Amirkhany; Wei Xiong (ISSCC, 2016)

A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process. - Anup P. Jose; Valentin Abramzon; Mohamed Elzeftawi; Michael Wang; Kyunglok Kim; Younghoon Song; Shiva Moballegh; Jalil Kamali; Amir Amirkhany (CICC, 2019)

Symbol spaced clock recovery for high speed links. - Gaurav Malhotra; Jalil Kamali (ICSPCS, 2019)

UBC2019 - A dataset of subjective image quality of head-mounted displays. - Vijayaraghavan Thirumalai; Javier Ribera; Jie Xiang; Junbin Zhang 002; Maryam Azimi; Jalil Kamali; Panos Nasiopoulos (Zenodo, 2020)

Baud rate pattern-adaptable dual loop clock recovery for high speed serial links. - Gaurav Malhotra; Jalil Kamali; Amir Amirkhany (ACSCC, 2021)