High-performance interconnects: an integration overview. - Robert H. Havemann; James A. Hutchby (Proc. IEEE, 2001)

Limits to binary logic switch scaling - a gedanken model. - Victor V. Zhirnov; Ralph K. Cavin III; James A. Hutchby; George Bourianoff (Proc. IEEE, 2003)

Boolean Logic and Alternative Information-Processing Devices. - George Bourianoff; Joe E. Brewer; Ralph K. Cavin III; James A. Hutchby; Victor V. Zhirnov (Computer, 2008)

Emerging Research Architectures. - Ralph K. Cavin III; James A. Hutchby; Victor V. Zhirnov; Joe E. Brewer; George Bourianoff (Computer, 2008)

Emerging Nanoscale Memory and Logic Devices: A Critical Assessment. - James A. Hutchby; Ralph K. Cavin III; Victor V. Zhirnov; Joe E. Brewer; George Bourianoff (Computer, 2008)

Nanoelectronics Research for Beyond CMOS Information Processing. - George Bourianoff; Michel Brillouët; Ralph K. Cavin III; Toshiro Hiramoto; James A. Hutchby; Adrian M. Ionescu; Ken Uchida (Proc. IEEE, 2010)

Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps. - Michel Brillouët; George Bourianoff; Ralph K. Cavin III; Toshiro Hiramoto; James A. Hutchby; Adrian M. Ionescu; Ken Uchida (Proc. IEEE, 2010)