IBM second-generation RISC machine organization. - H. B. Bakoglu; Gregory F. Grohoski; L. E. Thatcher; James A. Kahle; Charles R. Moore; David P. Tuttle; Warren E. Maule; W. R. Hardell Jr.; Dwain A. Hicks; M. Nguyenphu; Robert K. Montoye; W. T. Glover; et al. (Compcon, 1990)

A 2.2 W, 80 MHz superscalar RISC microprocessor. - Gianfranco Gerosa; Sonya Gary; Carl Dietz; Dac Pham; Kathy Hoover; Jose Alvarez; Hector Sanchez; Pete Ippolito; Tai Ngo; Suzanne Litch; Jim Eno; Jim Golab; et al. (IEEE J. Solid State Circuits, 1994)

The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. - Dac C. Pham; Erwin Behnen; Mark Bolliger; H. Peter Hofstee; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; Yoshio Masubuchi; Stephen D. Posluszny; Mack W. Riley; et al. (CICC, 2005)

The Cell Processor Architecture. - James A. Kahle (MICRO, 2005)

Introduction to the Cell multiprocessor. - James A. Kahle; Michael N. Day; H. Peter Hofstee; Charles R. Johns; Theodore R. Maeurer; David J. Shippy (IBM J. Res. Dev., 2005)

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. - Dac C. Pham; Hans-Werner Anderson; Erwin Behnen; Mark Bolliger; Sanjay Gupta; H. Peter Hofstee; Paul E. Harvey; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; et al. (ASP-DAC, 2006)

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. - Dac C. Pham; Tony Aipperspach; David Boerstler; Mark Bolliger; Rajat Chaudhry; Dennis Cox; Paul E. Harvey; H. Peter Hofstee; Charles R. Johns; Jim Kahle; Atsushi Kameyama; John M. Keaty; et al. (IEEE J. Solid State Circuits, 2006)

Cell architecture: key physical design features and methodology. - Jim Kahle (ISPD, 2007)

The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor. - Dieter F. Wendel; Ronald N. Kalla; Robert Cargnoni; Joachim G. Clabes; Joshua Friedrich; Roland Frech; James A. Kahle; Balaram Sinharoy; William J. Starke; Scott A. Taylor; Steve Weitzel; Sam G. Chu; et al. (ISSCC, 2010)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)

The design, deployment, and evaluation of the CORAL pre-exascale systems. - Sudharshan S. Vazhkudai; Bronis R. de Supinski; Arthur S. Bland; Al Geist; James C. Sexton; Jim Kahle; Christopher Zimmer 001; Scott Atchley; Sarp Oral; Don E. Maxwell; Verónica G. Vergara Larrea; Adam Bertsch; et al. (SC, 2018)

Summit and Sierra: Designing AI/HPC Supercomputers. - James A. Kahle; Jaime Moreno 002; Daniel Dreps (ISSCC, 2019)

Heterogeneous Computing Systems for Complex Scientific Discovery Workflows. - Christoph Hagleitner; Dionysios Diamantopoulos; Burkhard Ringlein; Constantinos Evangelinos; Charles R. Johns; Rong N. Chang; Bruce D'Amora; James A. Kahle; James C. Sexton; Michael Johnston; Edward Pyzer-Knapp; Chris Ward (DATE, 2021)

An Architecture for Heterogeneous High-Performance Computing Systems: Motivation and Requirements. - Christoph Hagleitner; Florian Auernhammer; James C. Sexton; Constantinos Evangelinos; Guerney Hunt; Christian Pinto; Michael Johnston; Charles R. Johns; Jim Kahle (JVA, 2023)