An overview of the BlueGene/L Supercomputer. - Narasimha R. Adiga; George Almási 001; George S. Almási; Yariv Aridor; Rajkishore Barik; Daniel K. Beece; Ralph Bellofatto; Gyan Bhanot; Randy Bickford; Matthias A. Blumrich; Arthur A. Bright; José R. Brunheroto; et al. (SC, 2002)

Blue Gene/L compute chip: Synthesis, timing, and physical design. - Arthur A. Bright; Ruud A. Haring; Marc Boris Dombrowa; Martin Ohmacht; Dirk Hoenicke; Sarabjeet Singh; James A. Marcella; Robert F. Lembach; Steve M. Douskey; Matthew R. Ellavsky; Christian G. Zoellin; Alan Gara (IBM J. Res. Dev., 2005)

Blue Gene/L compute chip: Control, test, and bring-up infrastructure. - Ruud A. Haring; Ralph Bellofatto; Arthur A. Bright; Paul Crumley; Marc Boris Dombrowa; Steve M. Douskey; Matthew R. Ellavsky; Balaji Gopalsamy; Dirk Hoenicke; Thomas A. Liebsch; James A. Marcella; Martin Ohmacht (IBM J. Res. Dev., 2005)

Blue Gene/L compute chip: Memory and Ethernet subsystem. - Martin Ohmacht; Reinaldo A. Bergamaschi; Subhrajit Bhattacharya; Alan Gara; Mark Giampapa; Balaji Gopalsamy; Ruud A. Haring; Dirk Hoenicke; David J. Krolak; James A. Marcella; Ben J. Nathanson; Valentina Salapura; et al. (IBM J. Res. Dev., 2005)

IBM POWER9 memory architectures for optimized systems. - William J. Starke; J. S. Dodson; Jeffrey Stuecheli; Eric Retter; Brad W. Michael; Stephen J. Powell; James A. Marcella (IBM J. Res. Dev., 2018)