Two-dimensional analysis of a merged BiPMOS device. - James B. Kuo; Geert P. Rosseel; Robert W. Dutton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Two-dimensional transient analysis of a collector-up ECL inverter. - James B. Kuo; Tsen-Shau Yang; Robert W. Dutton; Bruce A. Wooley (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

A coded block adaptive neural network system with a radical-partitioned structure for large-volume Chinese characters recognition. - Mark W. Mao; James B. Kuo (Neural Networks, 1992)

An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation. - Hwang-Cherng Chow; Wu-Shiung Feng; James B. Kuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI. - James B. Kuo; Hung-Pin Chen 001; H. J. Huang (ISCAS, 1993)

A Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique. - Mark W. Mao; B. Y. Chen; James B. Kuo (ISCAS, 1993)

A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unit. - James B. Kuo; H. J. Liao; H. P. Chen (IEEE J. Solid State Circuits, 1993)

A Radical-Partitioned Neural Network System Using a Modified Sigmoid Function and a Wight-Dotted Radical Selector for Large-Volume Chinese Characters Recognition VLSI. - James B. Kuo; B. Y. Chen; Mark W. Mao (ISCAS, 1994)

A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit. - James B. Kuo; K. W. Su; J. H. Lou (ISCAS, 1994)

A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable for VLSI using low-voltage BiCMOS technology. - James B. Kuo; K. W. Su; J. H. Lou; S. S. Chen; C. S. Chiang (IEEE J. Solid State Circuits, 1995)

A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. - James B. Kuo; K. W. Su; J. H. Lou (IEEE J. Solid State Circuits, 1995)

A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices. - Y. G. Chen; James B. Kuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI. - J. H. Lou; James B. Kuo (IEEE J. Solid State Circuits, 1997)

1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder. - J. H. Lou; James B. Kuo (ICECS, 1998)

A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. - Bo-Ting Wang; James B. Kuo (ISCAS, 2000)

A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell. - Perng-Fei Lin; James B. Kuo (IEEE J. Solid State Circuits, 2001)

A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques. - S. C. Liu; F. A. Wu; James B. Kuo (IEEE J. Solid State Circuits, 2001)

A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme. - Perng-Fei Lin; James B. Kuo (IEEE J. Solid State Circuits, 2002)

Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. - P. C. Chen; James B. Kuo (ISCAS (5), 2003)

A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI. - Hung-Pin Chen 001; James B. Kuo (ICECS, 2004)

Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited. - James B. Kuo (IWSOC, 2005)

Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. - Harry I. A. Chen; Edward K. W. Loo; James B. Kuo; Marek Syrzycki (PATMOS, 2007)

Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique. - Chih-Hsiang Lin; James B. Kuo (PATMOS, 2009)

Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications. - Chih-Hsiang Lin; James B. Kuo (ISCAS, 2010)

Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect. - H. J. Hung; James B. Kuo; D. Chen; Chih-Sheng Yeh (Microelectron. Reliab., 2010)

Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique. - Henry X. F. Huang; Steven R. S. Shen; James B. Kuo (PATMOS, 2011)

MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit. - Chen-Bo Hsu; Young Sik Hong; James B. Kuo (ICECS, 2014)

Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs. - Gregory J. Y. Lin; Chienbo B. Hsu; James B. Kuo (ISCAS, 2014)

MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits. - Chen-Bo Hsu; James B. Kuo (ISIC, 2014)

Parasitic BJT versus DIBL: Floating-body-related subthreshold characteristics of SOI NMOS device. - D. H. Lung; S. K. Hu; James B. Kuo; D. Chen; Y. J. Chen (ISIC, 2014)

Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS. - Chen-Bo Hsu; James B. Kuo (MWSCAS, 2014)