A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. - Shayan Shahramian; Behzad Dehlaghi; Joshua Liang; Ryan Bespalko; Dustin Dunwell; James Bailey 002; Bo Wang; Alireza Sharif Bakhtiar; Michael O'Farrell; Kerry Tang; Anthony Chan Carusone; David Cassan; et al. (ISSCC, 2019)

A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver. - James Bailey 002; Hossein Shakiba; Ehud Nir; Grigory Marderfeld; Peter Krotnev; Marc-Andre LaCroix; David Cassan (ISSCC, 2021)

A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s. - Behraz Vatankhahghadim; Nijwm Wary; James Bailey 002; Anthony Chan Carusone (IEEE Open J. Circuits Syst., 2021)

A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. - James Bailey 002; Hossein Shakiba; Ehud Nir; Grigory Marderfeld; Peter Krotnev; Marc-Andre LaCroix; David Cassan; Davide Tonietto (IEEE J. Solid State Circuits, 2022)