A low-cost, 300-MHz, RISC CPU with attached media processor. - Sribalan Santhanam; Allen J. Baum; David Bertucci; Mike Braganza; Kevin Broch; Todd Broch; James Burnette; Edward Chang; Kwong-Tak Chui; Dan Dobberpuhl; Paul M. Donahue; Joel Grodstein; et al. (IEEE J. Solid State Circuits, 1998)

Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology. - Brian Campbell 004; James Burnette; Naveen Javarappa; Vincent von Kaenel (CICC, 2007)

A 2GHz, 7W (max) 64b PowerTM Microprocessor Core. - Daniel Murray; James Burnette; Brian Campbell 004; Mark Chung; Bruce Fernandes; Subhendra Ghosh; Rajat Goel; Greg Hess; Hang Huang; Zhibin Huang; Naveen Javarappa; Pradeep Kanapathipillai; et al. (CICC, 2007)