InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers. - Marko Sokolich; Mary Y. Chen; Rajesh D. Rajavel; David H. Chow; Yakov Royter; Stephen Thomas III; Charles H. Fields; Binqiang Shi; Steven S. Bui; James Chingwei Li; Donald A. Hitko; Kenneth R. Elliott (IEEE J. Solid State Circuits, 2004)

100 GHz+ Gain-Bandwidth Differential Amplifiers in a Wafer Scale Heterogeneously Integrated Technology Using 250 nm InP DHBTs and 130 nm CMOS. - James Chingwei Li; Kenneth R. Elliott; David S. Matthews; Donald A. Hitko; Daniel Zehnder; Yakov Royter; Pamela R. Patterson; Tahir Hussain; Joseph F. Jensen (IEEE J. Solid State Circuits, 2009)

30.8 A 30GS/s double-switching track-and-hold amplifier with 19dBm IIP3 in an InP BiCMOS technology. - Timothy D. Gathman; Kristian N. Madsen; James Chingwei Li; Thomas C. Oh; James F. Buckwalter (ISSCC, 2014)

A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process. - Kristian N. Madsen; Timothy D. Gathman; Saeid Daneshgar; Thomas C. Oh; James Chingwei Li; James F. Buckwalter (IEEE J. Solid State Circuits, 2015)