Design tradeoffs for tiled CMP on-chip networks. - James D. Balfour; William J. Dally (ICS, 2006)

Register pointer architecture for efficient embedded processors. - JongSoo Park; Sung-Boem Park; James D. Balfour; David Black-Schaffer; Christos Kozyrakis; William J. Dally (DATE, 2007)

Flattened Butterfly Topology for On-Chip Networks. - John Kim 001; James D. Balfour; William J. Dally (IEEE Comput. Archit. Lett., 2007)

An Energy-Efficient Processor Architecture for Embedded Systems. - James D. Balfour; William J. Dally; David Black-Schaffer; Vishal Parikh; JongSoo Park (IEEE Comput. Archit. Lett., 2008)

Hierarchical Instruction Register Organization. - David Black-Schaffer; James D. Balfour; William J. Dally; Vishal Parikh; JongSoo Park (IEEE Comput. Archit. Lett., 2008)

Efficient Embedded Computing. - William J. Dally; James D. Balfour; David Black-Schaffer; James Chen; R. Curtis Harting; Vishal Parikh; JongSoo Park; David Sheffield (Computer, 2008)

Elastic-buffer flow control for on-chip networks. - George Michelogiannakis; James D. Balfour; William J. Dally (HPCA, 2009)

Operand Registers and Explicit Operand Forwarding. - James D. Balfour; R. C. Halting; William J. Dally (IEEE Comput. Archit. Lett., 2009)

Fine-grain dynamic instruction placement for L0 scratch-pad memory. - JongSoo Park; James D. Balfour; William J. Dally (CASES, 2010)

A detailed and flexible cycle-accurate Network-on-Chip simulator. - Nan Jiang 009; Daniel U. Becker; George Michelogiannakis; James D. Balfour; Brian Towles; David E. Shaw; John Kim 001; William J. Dally (ISPASS, 2013)

Author retrospective for design tradeoffs for tiled CMP on-chip networks. - William J. Dally; James D. Balfour (ICS 25th Anniversary, 2014)