Scanning the issue. - Kenneth A. Pickar; James D. Meindl (Proc. IEEE, 1986)

Offset word-line architecture for scaling DRAMs to the gigabit level. - Roy E. Scheuerlein; James D. Meindl (IEEE J. Solid State Circuits, 1988)

Design and Test Automation-Gigascale Integration (GSI) in the 21st Century. - James D. Meindl (ICCD, 1991)

Gigascale integration (GSI) technology. - James D. Meindl (SC, 1991)

An analytical threshold voltage and subthreshold current model for short-channel MESFETs. - Vivek K. De; James D. Meindl (IEEE J. Solid State Circuits, 1993)

An analytical threshold voltage and subthreshold current model for short-channel AlGaAs/GaAs MODFETs. - Vivek K. De; James D. Meindl (IEEE J. Solid State Circuits, 1993)

Analytical drain current models for AlGaAs/GaAs MODFET's including subthreshold conduction. - Vivek K. De; James D. Meindl (IEEE J. Solid State Circuits, 1993)

Short channel models and scaling limits of SOI and bulk MOSFETs. - Bhavna Agrawal; Vivek K. De; Joseph M. Pimbley; James D. Meindl (IEEE J. Solid State Circuits, 1994)

Low power microelectronics: retrospect and prospect. - James D. Meindl (Proc. IEEE, 1995)

Circuit techniques for low-power CMOS GSI. - Azeez J. Bhavnagarwala; Vivek De; Blanca Austin; James D. Meindl (ISLPED, 1996)

A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). - Vivek De; James D. Meindl (ISLPED, 1996)

Effects of random MOSFET parameter fluctuations on total power consumption. - Xinghai Tang; Vivek De; James D. Meindl (ISLPED, 1996)

A history of low power electronics: how it began and where it's headed. - James D. Meindl (ISLPED, 1997)

Intrinsic MOSFET parameter fluctuations due to random dopant placement. - Xinghai Tang; Vivek De; James D. Meindl (IEEE Trans. Very Large Scale Integr. Syst., 1997)

On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule. - Payman Zarkesh-Ha; Jeffrey A. Davis; William Loh; James D. Meindl (CICC, 1998)

Minimum supply voltage for bulk Si CMOS GSI. - Azeez J. Bhavnagarwala; Blanca Austin; James D. Meindl (ISLPED, 1998)

Exploring Microprocessor Architectures for Gigascale Integration. - Lucian Codrescu; Mondira Deb Pant; Tarek M. Taha; John Eble; D. Scott Wills; James D. Meindl (ARVLSI, 1999)

XXI Century Gigascale Integration (GSI) : The Interconnect Problem. - James D. Meindl (ARVLSI, 1999)

Characterization and modeling of clock skew with process variations. - Payman Zarkesh-Ha; Tony Mule; James D. Meindl (CICC, 1999)

A physical alpha-power law MOSFET model. - Keith A. Bowman; Blanca Austin; John C. Eble; Xinghai Tang; James D. Meindl (IEEE J. Solid State Circuits, 1999)

CMOS system-on-a-chip voltage scaling beyond 50nm. - Azeez J. Bhavnagarwala; Blanca Austin; Ashok Kapoor; James D. Meindl (ACM Great Lakes Symposium on VLSI, 2000)

Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. - Raguraman Venkatesan; Jeffrey A. Davis; Keith A. Bowman; James D. Meindl (ISLPED, 2000)

Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). - Jeffrey A. Davis; Raguraman Venkatesan; Keith A. Bowman; James D. Meindl (SLIP, 2000)

Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. - James W. Joyner; Payman Zarkesh-Ha; Jeffrey A. Davis; James D. Meindl (SLIP, 2000)

Prediction of interconnect fan-out distribution using Rent's rule. - Payman Zarkesh-Ha; Jeffrey A. Davis; William Loh; James D. Meindl (SLIP, 2000)

The fundamental limit on binary switching energy for terascale integration (TSI). - James D. Meindl; Jeffrey A. Davis (IEEE J. Solid State Circuits, 2000)

A minimum total power methodology for projecting limits on CMOS GSI. - Azeez J. Bhavnagarwala; Blanca Austin; Keith A. Bowman; James D. Meindl (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Heterogeneous architecture models for interconnect-motivated system design. - Sek M. Chai; Tarek M. Taha; D. Scott Wills; James D. Meindl (IEEE Trans. Very Large Scale Integr. Syst., 2000)

A compact physical via blockage model. - Qiang Chen; Jeffrey A. Davis; Payman Zarkesh-Ha; James D. Meindl (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. - Payman Zarkesh-Ha; Jeffrey A. Davis; James D. Meindl (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Impact of within-die parameter fluctuations on future maximum clock frequency distributions. - Keith A. Bowman; James D. Meindl (CICC, 2001)

Interconnect-centric Array Architectures for Minimum SRAM Access Time. - Azeez J. Bhavnagarwala; Stephen V. Kosonocky; James D. Meindl (ICCD, 2001)

On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. - Martin Saint-Laurent; Madhavan Swaminathan; James D. Meindl (ICCD, 2001)

The impact of intrinsic device fluctuations on CMOS SRAM cell stability. - Azeez J. Bhavnagarwala; Xinghai Tang; James D. Meindl (IEEE J. Solid State Circuits, 2001)

Interconnect limits on gigascale integration (GSI) in the 21st century. - Jeffery A. Davis; Raguraman Venkatesan; Alan Kaloyeros; Michael Beylansky; Shukri J. Souri; Kaustav Banerjee; Krishna C. Saraswat; Arifur Rahman; Rafael Reif; James D. Meindl (Proc. IEEE, 2001)

Special issue on limits of semiconductor technology. - James D. Meindl (Proc. IEEE, 2001)

Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. - Lucian Codrescu; D. Scott Wills; James D. Meindl (IEEE Trans. Computers, 2001)

Impact of three-dimensional architectures on interconnects in gigascale integration. - James W. Joyner; Raguraman Venkatesan; Payman Zarkesh-Ha; Jeffrey A. Davis; James D. Meindl (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). - Raguraman Venkatesan; Jeffrey A. Davis; Keith A. Bowman; James D. Meindl (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection. - Muhannad S. Bakir; Hollie A. Reed; Anthony V. Mulé; Paul A. Kohl; Kevin P. Martin; James D. Meindl (CICC, 2002)

A physical model for the transient response of capacitively loaded distributed rlc interconnects. - Raguraman Venkatesan; Jeffrey A. Davis; James D. Meindl (DAC, 2002)

A compact delay model for series-connected MOSFETs. - Kaveh Shakeri; James D. Meindl (ACM Great Lakes Symposium on VLSI, 2002)

Low-power circuit advantages of the scaled accumulation FET. - R. Murali; Lihui Wang; Blanca Austin; James D. Meindl (ISCAS (5), 2002)

Temperature Variable Supply Voltage for Power Reduction. - Kaveh Shakeri; James D. Meindl (ISVLSI, 2002)

Interconnect opportunities for gigascale integration. - James D. Meindl; Jeffrey A. Davis; Payman Zarkesh-Ha; Chirag S. Patel; Kevin P. Martin; Paul A. Kohl (IBM J. Res. Dev., 2002)

Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. - Keith A. Bowman; Steven G. Duvall; James D. Meindl (IEEE J. Solid State Circuits, 2002)

Electrical and optical clock distribution networks for gigascale microprocessors. - A. V. Mule; Elias N. Glytsis; Thomas K. Gaylord; James D. Meindl (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Beyond Moore's Law: the interconnect era. - James D. Meindl (Comput. Sci. Eng., 2003)

Interconnect Opportunities for Gigascale Integration. - James D. Meindl (IEEE Micro, 2003)

Modeling technology impact on cluster microprocessor performance. - Lucian Codrescu; S. Nugent; James D. Meindl; D. Scott Wills (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Relative inductance extraction method. - Kaveh Shakeri; James D. Meindl (CICC, 2004)

Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution. - Kaveh Shakeri; Muhannad S. Bakir; James D. Meindl (SoCC, 2004)

Global interconnect design in a three-dimensional system-on-a-chip. - James W. Joyner; Payman Zarkesh-Ha; James D. Meindl (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects. - Hiren D. Thacker; James D. Meindl (ITC, 2006)

Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems. - Muhannad S. Bakir; Bing Dang; James D. Meindl (CICC, 2007)

Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots. - Gang Huang; Deepak C. Sekar; Azad Naeemi; Kaveh Shakeri; James D. Meindl (CICC, 2007)

Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. - Azad Naeemi; Reza Sarvari; James D. Meindl (DAC, 2007)

IntSim: A CAD tool for optimization of multilevel interconnect networks. - Deepak C. Sekar; Azad Naeemi; Reza Sarvari; Jeffrey A. Davis; James D. Meindl (ICCAD, 2007)

Carbon nanotube interconnects. - Azad Naeemi; James D. Meindl (ISPD, 2007)

3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation. - Muhannad S. Bakir; Calvin King; Deepak C. Sekar; Hiren D. Thacker; Bing Dang; Gang Huang; Azad Naeemi; James D. Meindl (CICC, 2008)

Physical models for electron transport in graphene nanoribbons and their junctions. - Azad Naeemi; James D. Meindl (ICCAD, 2008)

Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method. - Kaveh Shakeri; James D. Meindl (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Nanoelectronics in retrospect, prospect and principle. - James D. Meindl; Azad Naeemi; Muhannad S. Bakir; R. Murali (ISSCC, 2010)