Cache simulation for irregular memory traffic on multi-core CPUs: Case study on performance models for sparse matrix-vector multiplication. - James D. Trotter; Johannes Langguth; Xing Cai (J. Parallel Distributed Comput., 2020)

On Memory Traffic and Optimisations for Low-order Finite Element Assembly Algorithms on Multi-core CPUs. - James D. Trotter; Xing Cai; Simon W. Funke (ACM Trans. Math. Softw., 2022)

Performance Prediction for Sparse Matrix Vector Multiplication Using Structure-Dependent Features. - Konstantin Pogorelov; James D. Trotter; Johannes Langguth (Euro-Par Workshops (1), 2023)

Modelling Data Locality of Sparse Matrix-Vector Multiplication on the A64FX. - Sergej Breiter; James D. Trotter; Karl Fürlinger (SC Workshops, 2023)

Bringing Order to Sparsity: A Sparse Matrix Reordering Study on Multicore CPUs. - James D. Trotter; Sinan Ekmekçibasi; Johannes Langguth; Tugba Torun; Emre Düzakin; Aleksandar Ilic; Didem Unat (SC, 2023)

Targeting performance and user-friendliness: GPU-accelerated finite element computation with automated code generation in FEniCS. - James D. Trotter; Johannes Langguth; Xing Cai (Parallel Comput., 2023)