A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage. - Kai-Yap Toh; Ching-Te Chuang; Tze-Chiang Chen; James D. Warnock (IEEE J. Solid State Circuits, 1989)

Multigigahertz voltage-controlled oscillators in advanced silicon bipolar technology. - Mehmet Soyuer; James D. Warnock (IEEE J. Solid State Circuits, 1992)

12.8-ps 1.0-mW charge-buffered active pull-down NTL circuit. - Kenneth Chin; Ching-Te Chuang; James D. Warnock (IEEE J. Solid State Circuits, 1992)

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications. - Ghavam G. Shahidi; James D. Warnock; James Comfort; Stephen E. Fischer; Patricia A. McFarland; Alexandre Acovic; Terry I. Chappell; Barbara A. Chappell; Tak H. Ning; Carl J. Anderson; Robert H. Dennard; Jack Y.-C. Sun; et al. (IBM J. Res. Dev., 1995)

High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor. - James D. Warnock; Leon J. Sigal; Brian W. Curran; Yuen H. Chan (ICCD, 1997)

Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor. - Leon J. Sigal; James D. Warnock; Brian W. Curran; Yuen H. Chan; Peter J. Camporese; Mark D. Mayo; William V. Huott; Daniel R. Knebel; Ching-Te Chuang; James P. Eckhardt; Philip T. Wu (IBM J. Res. Dev., 1997)

A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. - Charles F. Webb; Carl J. Anderson; Leon J. Sigal; Kenneth L. Shepard; John S. Liptay; James D. Warnock; Brian W. Curran; Barry Krumm; Mark D. Mayo; Peter J. Camporese; Eric M. Schwarz; Mark S. Farrell; et al. (IEEE J. Solid State Circuits, 1997)

The circuit and physical design of the POWER4 microprocessor. - James D. Warnock; John M. Keaty; John G. Petrovick; Joachim G. Clabes; Charles J. Kircher; Byron Krauter; Phillip J. Restle; Brian A. Zoric; Carl J. Anderson (IBM J. Res. Dev., 2002)

The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. - Dac C. Pham; Erwin Behnen; Mark Bolliger; H. Peter Hofstee; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; Yoshio Masubuchi; Stephen D. Posluszny; Mack W. Riley; et al. (CICC, 2005)

Cell Processor Low-Power Design Methodology. - Daniel L. Stasiak; Rajat Chaudhry; Dennis Cox; Stephen D. Posluszny; James D. Warnock; Steve Weitzel; Dieter F. Wendel; Michael Wang 001 (IEEE Micro, 2005)

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. - Dac C. Pham; Hans-Werner Anderson; Erwin Behnen; Mark Bolliger; Sanjay Gupta; H. Peter Hofstee; Paul E. Harvey; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; et al. (ASP-DAC, 2006)

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. - Dac C. Pham; Tony Aipperspach; David Boerstler; Mark Bolliger; Rajat Chaudhry; Dennis Cox; Paul E. Harvey; H. Peter Hofstee; Charles R. Johns; Jim Kahle; Atsushi Kameyama; John M. Keaty; et al. (IEEE J. Solid State Circuits, 2006)

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor. - James D. Warnock; Dieter F. Wendel; Tony Aipperspach; Erwin Behnen; Robert A. Cordes; Sang H. Dhong; Koji Hirairi; Hiroaki Murakami; Shohji Onishi; Dac C. Pham; Jürgen Pille; Stephen D. Posluszny; et al. (IEEE J. Solid State Circuits, 2006)

Cell Broadband Engine processor: Design and implementation. - Mack W. Riley; James D. Warnock; Dieter F. Wendel (IBM J. Res. Dev., 2007)

Introduction to the Special Issue on the 2006 IEEE International Solid-State Circuits Conference. - James D. Warnock; William Bidermann; Albert van der Werf; Katsuyuki Sato (IEEE J. Solid State Circuits, 2007)

An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. - Rouwaida Kanj; Rajiv V. Joshi; Chad Adams; James D. Warnock; Sani R. Nassif (ICCAD, 2009)

POWER7TM local clocking and clocked storage elements. - James D. Warnock; Leon J. Sigal; Dieter F. Wendel; K. Paul Muller; Joshua Friedrich; Victor V. Zyuban; Ethan H. Cannon; A. J. KleinOsowski (ISSCC, 2010)

Design, CAD and technology challenges for future processors: 3D perspectives. - Jeff Burns; Gary Carpenter; Eren Kursun; Ruchir Puri; James D. Warnock; Michael Scheuermann (DAC, 2011)

Circuit design challenges at the 14nm technology node. - James D. Warnock (DAC, 2011)

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system. - James D. Warnock; Y. Chan; William V. Huott; Sean M. Carey; Michael F. Fee; Huajun Wen; Mary Jo Saccamango; Frank Malgioglio; Patrick J. Meaney; Donald W. Plass; Yuen H. Chan; Mark D. Mayo; et al. (ISSCC, 2011)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)

The zEnterprise 196 System and Microprocessor. - Brian W. Curran; Lee Eisen; Eric M. Schwarz; Pak-kin Mak; James D. Warnock; Patrick J. Meaney; Michael F. Fee (IEEE Micro, 2011)

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. - James D. Warnock; Yiu-Hing Chan; Sean M. Carey; Huajun Wen; Patrick J. Meaney; Guenter Gerwig; Howard H. Smith; Yuen H. Chan; John Davis; Paul Bunce; Antonio Pelella; Daniel Rodko; et al. (IEEE J. Solid State Circuits, 2012)

Circuit and PD challenges at the 14nm technology node. - James D. Warnock (ISPD, 2013)

5.5GHz system z microprocessor and multi-chip module. - James D. Warnock; Yuen H. Chan; Hubert Harrer; David L. Rude; Ruchir Puri; Sean M. Carey; Gerard Salem; Guenter Mayer; Yiu-Hing Chan; Mark D. Mayo; Adam Jatkowski; Gerald Strevig; et al. (ISSCC, 2013)

Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module. - James D. Warnock; Yuen H. Chan; Hubert Harrer; Sean M. Carey; Gerard Salem; Doug Malone; Ruchir Puri; Jeffrey A. Zitz; Adam Jatkowski; Gerald Strevig; Ayan Datta; Anne Gattiker; et al. (IEEE J. Solid State Circuits, 2014)

A case study of electromigration reliability: From design point to system operations. - Baozhen Li; K. Paul Muller; James D. Warnock; Leon J. Sigal; Dinesh Badami (IRPS, 2015)

4.1 22nm Next-generation IBM System z microprocessor. - James D. Warnock; Brian W. Curran; John Badar; Gregory Fredeman; Donald W. Plass; Yuen H. Chan; Sean M. Carey; Gerard Salem; Friedrich Schroeder; Frank Malgioglio; Guenter Mayer; Christopher J. Berry; et al. (ISSCC, 2015)

IBM z13 circuit design and methodology. - James D. Warnock; Christopher J. Berry; Michael H. Wood; Leon J. Sigal; Yun-Chan Myung; Guenter Mayer; Mark D. Mayo; Y. Chan; Frank Malgioglio; Gerald Strevig; Charudhattan Nagarajan; Sean M. Carey; et al. (IBM J. Res. Dev., 2015)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

Design-synthesis co-optimisation using skewed and tapered gates. - Ayan Datta; James D. Warnock; Ankur Shukla; Saurabh Gupta; Yiu H. Chan; Karthik Mohan; Charudhattan Nagarajan (DATE, 2016)

IBM z14™: 14nm microprocessor for the next-generation mainframe. - Christopher J. Berry; James D. Warnock; John Isakson; John Badar; Brian Bell 001; Frank Malgioglio; Guenter Mayer; Dina Hamid; Jesse Surprise; David Wolpert 001; Ofer Geva; Bill Huott; et al. (ISSCC, 2018)

Impact of Device Aging on Early Mode Failures in Pulsed Latches. - Ankur Shukla; Rahul M. Rao; James D. Warnock (VLSID, 2018)

IBM z14 design methodology enhancements in the 14-nm technology node. - Christopher J. Berry; James D. Warnock; John Badar; Dean G. Bair; Erwin Behnen; Brian Bell 001; Alper Buyuktosunoglu; Chris Cavitt; Pierce Chuang; Ofer Geva; Dina Hamid; John Isakson; et al. (IBM J. Res. Dev., 2018)

IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors. - David Wolpert 001; Erwin Behnen; Leon J. Sigal; Yuen H. Chan; Gustavo Enrique Téllez; Douglas Bradley; Richard E. Serton; Rajesh Veerabhadraiah; William Ansley; Andrew Bianchi; Nagu Dhanwada; Sungjae Lee; et al. (IBM J. Res. Dev., 2018)