Design validation of .18 μm 1 GHz cache and register arrays. - Doug Malone; Paul Bunce; Joe DellaPietro; John Davis; James Dawson; Thomas J. Knips; Don Plass; Phil Pritzlaff; Kenneth Reyer (CICC, 2000)

Design and implementation of the POWER5 microprocessor. - Joachim G. Clabes; Joshua Friedrich; Mark Sweet; Jack DiLullo; Sam G. Chu; Donald W. Plass; James Dawson; Paul Muench; Larry Powell; Michael S. Floyd; Balaram Sinharoy; Mike Lee; et al. (DAC, 2004)

Implicit media frames: Automated analysis of public debate on artificial sweeteners - Iina Hellsten; James Dawson; Loet Leydesdorff (CoRR, 2010)